IP Library Granted Patent US 8,133,762
Granted Patent B2
US 8,133,762 · App. 12/406,049 · Granted Mar 13, 2012

Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core

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Quick Facts
Patent No.
US 8,133,762
App. No.
12/406,049
Granted
Mar 13, 2012
Kind
B2
Abstract

A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

Claims (63)

1. A method of making a semiconductor device, comprising:

providing a sacrificial substrate;

depositing an interface layer over the sacrificial substrate;

forming a first conductive layer over the interface layer;

forming a first polymer pillar over the first conductive layer;

forming a second conductive layer over the first polymer pillar to create a first conductive pillar with inner polymer core;

mounting a semiconductor die or component over the sacrificial substrate;

depositing an encapsulant over the semiconductor die or component and around the first conductive pillar;

forming a first interconnect structure over a first side of the encapsulant, the first interconnect structure being electrically connected to the first conductive pillar;

removing the sacrificial substrate and interface layer; and

forming a second interconnect structure over a second side of the encapsulant opposite the first interconnect structure, the second interconnect structure being electrically connected to the first conductive pillar.

2. The method of claim 1 , wherein the first interconnect structure includes an integrated passive device.

3. The method of claim 1 , further including:

forming a second polymer pillar over a contact pad of the semiconductor die; and

forming the second conductive layer over the second polymer pillar to create a second conductive pillar with inner polymer core.

4. The method of claim 1 , further including:

stacking a plurality of semiconductor devices; and

electrically connecting the semiconductor devices through the first and second interconnect structures and first conductive pillar.

5. The method of claim 1 , wherein forming the first interconnect structure includes:

forming a first insulating layer over the encapsulant;

forming a third conductive layer over the first insulating layer, the third conductive layer being electrically connected to the first conductive pillar; and

forming a second insulating layer over the third conductive layer.

6. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over the substrate;

forming a first polymer pillar over the first conductive layer;

forming a second conductive layer over the first polymer pillar to create a first conductive pillar with an inner stress-relief core;

mounting a semiconductor die or component over the substrate;

depositing an encapsulant over the semiconductor die or component and around the first conductive pillar;

forming a first interconnect structure over a first side of the encapsulant, the first interconnect structure being electrically connected to the first conductive pillar; and

forming a second interconnect structure over a second side of the encapsulant opposite the first interconnect structure, the second interconnect structure being electrically connected to the first conductive pillar.

7. The method of claim 6 , wherein the first interconnect structure includes an integrated passive device.

8. The method of claim 7 , wherein the integrated passive device includes a capacitor, resistor, or inductor.

9. The method of claim 6 , wherein forming the first interconnect structure includes:

forming a first insulating layer over the encapsulant;

forming a third conductive layer over the first insulating layer, the third conductive layer being electrically connected to the first conductive pillar; and

forming a second insulating layer over the third conductive layer.

10. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over the substrate;

forming a first polymer pillar over the first conductive layer;

forming a second conductive layer over the first polymer pillar to create a first conductive pillar with an inner stress-relief core;

mounting a semiconductor die or component over the substrate;

depositing an encapsulant over the semiconductor die or component and around the first conductive pillar; and

forming a first interconnect structure over a first side of the encapsulant, the first interconnect structure being electrically connected to the first conductive pillar.

11. The method of claim 10 , further including forming a second interconnect structure over a second side of the encapsulant opposite the first interconnect structure, the second interconnect structure being electrically connected to the first conductive pillar.

12. The method of claim 10 , wherein the first interconnect structure includes an integrated passive device.

13. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over the substrate;

forming a first polymer pillar over the first conductive layer;

forming a second conductive layer over the first polymer pillar to create a first conductive pillar with an inner stress-relief core;

mounting a semiconductor die or component over the substrate; and

depositing an encapsulant over the semiconductor die or component and around the first conductive pillar.

14. The method of claim 13 , further comprising forming a first interconnect structure over a first side of the encapsulant.

15. The method of claim 14 , wherein the first interconnect structure is electrically connected to the first conductive pillar.

16. The method of claim 15 , wherein the first interconnect structure includes an IPD.

17. The method of claim 16 , further comprising forming a second interconnect structure over a second side of the encapsulant opposite the first interconnect structure.

18. The method of claim 17 , wherein the second interconnect structure is electrically connected to the first conductive pillar.

19. The method of claim 18 , wherein providing a substrate comprises providing a sacrificial substrate.

20. The method of claim 19 , further comprising removing the sacrificial substrate.

21. The method of claim 20 , further comprising depositing an interface layer over the sacrificial substrate.

22. The method of claim 21 , further comprising removing the interface layer.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0474 ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 8, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064842/0046 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38378 FRAME: 0280) Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0474 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →