Stacked integrated circuit and package system and method for manufacturing thereof
View Patent ↗A method for manufacturing a stacked integrated circuit and package system includes: attaching a high temperature resistant layer on a top substrate; mounting a first top integrated circuit on the high temperature resistant layer; mounting a second top integrated circuit on the first top integrated circuit; molding an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate; mounting a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit; mounting a fourth top integrated circuit on the third top integrated circuit; molding an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate; forming top electrical connectors on a lower surface of the top substrate; and mounting a bottom package to the top electrical connectors.
1. A method for manufacturing a stacked integrated circuit and package system comprising:
attaching a high temperature resistant layer on a top substrate;
mounting a first top integrated circuit on the high temperature resistant layer and the first top IC is within the top substrate;
mounting a second top integrated circuit on the first top integrated circuit;
molding an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate;
mounting a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit;
mounting a fourth top integrated circuit on the third top integrated circuit;
molding an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate;
forming top electrical connectors on a lower surface of the top substrate so a flattened side of the electrical connector is coplanar with a side of the first top integrated circuit and a side of the third top integrated circuit; and
mounting a bottom package to the top electrical connectors.
2. The method as claimed in claim 1 wherein mounting the bottom package further comprises:
attaching a temporary layer on a bottom substrate;
mounting a first bottom integrated circuit on the temporary layer; and
mounting a second bottom integrated circuit on the first bottom integrated circuit.
3. The method as claimed in claim 1 wherein mounting the bottom package further comprises:
attaching a temporary layer on a bottom substrate; and
mounting a bottom integrated circuit on the temporary layer.
4. The method as claimed in claim 1 wherein mounting the bottom package further comprises forming bottom electrical connectors with smaller dimensions than the top electrical connectors dimensions.
5. The method as claimed in claim 1 wherein attaching the first high temperature resistant layer further comprises attaching the first high temperature resistant layer on an upper surface of the top substrate.
6. A stacked integrated circuit and package system comprising:
a first top integrated circuit located within a top substrate;
a second top integrated circuit located on a surface opposite of an active area of the top substrate of the first top integrated circuit;
top electrical connectors on the lower surface of the top substrate so a flattened side of the electrical connector is coplanar with a side of the first top integrated circuit and a side of the second top integrated circuit; and
a bottom package connected to the top electrical connectors, wherein the bottom package further comprises bottom electrical connectors with smaller dimensions that the top electrical connectors dimensions.
7. The system as claimed in claim 6 further comprising a high temperature resistant layer on the top substrate.
8. The system as claimed in claim 6 further comprising a temporary layer on the bottom substrate.
9. The system as claimed in claim 6 wherein the top electrical connectors further comprise a solder ball grid array.
10. A stacked integrated circuit and package system comprising:
a high temperature resistant layer on a top substrate;
a first top integrated circuit on the high temperature resistant layer and the first top integrated circuit located within the top substrate;
a second top integrated circuit on the first top integrated circuit;
an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate;
a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit;
a fourth top integrated circuit on the third top integrated circuit;
an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate;
top electrical connectors on a lower surface of the top substrate; and
a bottom package mounted to the top electrical connectors, wherein the bottom package further comprises bottom electrical connectors with smaller dimensions than the top electrical connectors dimensions.
11. The system as claimed in claim 10 wherein the bottom package further comprises:
a temporary layer on a bottom substrate;
a first bottom integrated circuit on the temporary layer; and
a second bottom integrated circuit on the first bottom integrated circuit.
12. The system as claimed in claim 10 wherein the bottom package further comprises:
a temporary layer on a bottom substrate; and
a bottom integrated circuit on the temporary layer.
13. The system as claimed in claim 10 wherein the first high temperature resistant layer further comprises the first high temperature resistant layer on an upper surface of the top substrate.