Patent Assignment
Reel/Frame 065236/0730
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0272. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Recorded: 2023-08-31
Received: 2023-10-16
Pages: 11
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 53, SINGAPORE, SGX, SINGAPORE
Covered Applications
(73)
STACKED INTEGRATED CIRCUIT AND PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/006,278
→
EMBEDDED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/964,638
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING THROUGH SILICON VIA WITH DIRECT INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/949,835
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER LEVEL GROUND PLANE AND POWER RING
App. No. 12/905,797
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WLP WITH SEMICONDUCTOR DIE EMBEDDED WITHIN PENETRABLE ENCAPSULANT BETWEEN TSV INTERPOSERS
App. No. 12/876,425
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH SIDE-BY-SIDE AND OFFSET STACKING AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/871,031
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED INTERCONNECT LAYER FOR STACKED SEMICONDUCTOR DIE
App. No. 12/870,696
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER-LEVEL MULTI-ROW ETCHED LEADFRAME WITH BASE LEADS AND EMBEDDED SEMICONDUCTOR DIE
App. No. 12/857,395
→
SEMICONDUCTOR DEVICE HAVING ELECTRICAL DEVICES MOUNTED TO IPD STRUCTURE AND METHOD OF SHIELDING ELECTROMAGNETIC INTERFERENCE
App. No. 12/830,390
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/792,629
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED EMI SHIELDING FRAME WITH CAVITIES CONTAINING PENETRABLE MATERIAL OVER SEMICONDUCTOR DIE
App. No. 12/792,066
→
SEMICONDUCTOR DEVICE AND METHOD OF STACKING SAME SIZE SEMICONDUCTOR DIE ELECTRICALLY CONNECTED THROUGH CONDUCTIVE VIA FORMED AROUND PERIPHERY OF THE DIE
App. No. 12/788,785
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
App. No. 12/782,992
→
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/777,023
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR 3-D DEVICES USING ENCAPSULANT FOR STRUCTURAL SUPPORT
App. No. 12/775,188
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM AND METHOD FOR MAKING THEREOF
App. No. 12/772,128
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON DIFFERENT HEIGHT TRACES
App. No. 12/720,029
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED CONDUCTOR AND METHOD OF MANUFACTURE THEREOF
App. No. 12/714,320
→
METHOD OF FORMING QUAD FLAT PACKAGE
App. No. 12/703,450
→
QUAD FLAT PACKAGE
App. No. 12/703,461
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED-DOWN RDL AND RECESSED THV IN PERIPHERAL REGION OF THE DEVICE
App. No. 12/641,958
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/608,587
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND MANUFACTURING METHOD THEREOF
App. No. 12/578,797
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPOSITE BUMP-ON-LEAD INTERCONNECTION
App. No. 12/562,414
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/560,312
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIE AND PACKAGE COMBINATION
App. No. 12/544,555
→
SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURES
App. No. 12/540,174
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A DUAL SUBSTRATE PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/488,555
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE BETWEEN NON-LINEAR PORTIONS OF CONDUCTIVE LAYERS
App. No. 12/484,146
→
METHOD OF FORMING STRESS RELIEF LAYER BETWEEN DIE AND INTERCONNECT STRUCTURE
App. No. 12/481,404
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERCONNECT STRUCTURE WITH TSV USING ENCAPSULANT FOR STRUCTURAL SUPPORT
App. No. 12/480,317
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM FIXED RELATIVE TO INTERCONNECT STRUCTURE FOR ALIGNMENT OF SEMICONDUCTOR DIE
App. No. 12/476,447
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER INTERCONNECTIONS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/473,253
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND HEAT SPREADER WITH OPENINGS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/423,099
→
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING PRE-FABRICATED SHIELDING FRAME OVER SEMICONDUCTOR DIE
App. No. 12/409,142
→
SEMICONDUCTOR DIE AND METHOD OF FORMING NOISE ABSORBING REGIONS BETWEEN THVS IN PERIPHERAL REGION OF THE DIE
App. No. 12/404,069
→
SEMICONDUCTOR DEVICE AND METHOD OF INTEGRATING BALUN AND RF COUPLER ON A COMMON SUBSTRATE
App. No. 12/403,234
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A DUAL BOARD-ON-CHIP STRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/398,466
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SLUG
App. No. 12/398,163
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING ASYMMETRIC ENCAPSULATION STRUCTURES AND METHOD OF MANUFACTURE THEREOF
App. No. 12/328,762
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI LEVEL CONTACT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/273,547
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED PAD AND METHOD OF MANUFACTURE THEREOF
App. No. 12/272,751
→
SEMICONDUCTOR PACKAGE SYSTEM WITH THROUGH SILICON VIA INTERPOSER
App. No. 12/239,715
→
LEADLESS SEMICONDUCTOR CHIP CARRIER SYSTEM
App. No. 12/205,841
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER
App. No. 12/198,491
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/194,506
→
BALL GRID ARRAY PACKAGE STACKING SYSTEM
App. No. 12/141,059
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLEXIBLE SUBSTRATE AND RECESSED PACKAGE
App. No. 12/136,002
→
SEMICONDUCTOR DEVICE AND METHOD OF SHIELDING SEMICONDUCTOR DIE FROM INTER-DEVICE INTERFERENCE
App. No. 12/133,216
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INSULATOR OVER CIRCUITRY
App. No. 12/126,684
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELD AND TIE BAR
App. No. 12/124,793
→
THROUGH HOLE VIAS AT SAW STREETS INCLUDING PROTRUSIONS OR RECESSES FOR INTERCONNECTION
App. No. 12/057,199
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT STRUCTURE UNDER WIRE-IN-FILM ADHESIVE
App. No. 12/055,634
→
SYSTEM FOR SOLDER BALL INNER STACKING MODULE CONNECTION
App. No. 12/046,369
→
SEMICONDUCTOR PACKAGE HAVING SEMICONDUCTOR DIE WITH INTERNAL VERTICAL INTERCONNECT STRUCTURE AND METHOD THEREFOR
App. No. 12/044,803
→
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES
App. No. 12/037,291
→
SEMICONDUCTOR DEVICE AND METHOD OF SUPPORTING A WAFER DURING BACKGRINDING AND REFLOW OF SOLDER BUMPS
App. No. 12/036,000
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERPOSER
App. No. 11/966,219
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE INTEGRATION
App. No. 11/957,845
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING
App. No. 11/954,603
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SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SIMILAR STRUCTURE FOR TOP AND BOTTOM BONDING PADS
App. No. 11/952,502
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DIE
App. No. 11/863,700
→
SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
App. No. 11/859,416
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH GROUND BONDS
App. No. 11/766,785
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIFFERENT MOLD LOCKING FEATURES
App. No. 11/749,693
→
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RECESS
App. No. 11/618,807
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INTEGRATED CIRCUIT PACKAGE WITH TOP PAD
App. No. 11/618,805
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
App. No. 11/532,510
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK
App. No. 11/532,509
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING WAFER LEVEL SPACER
App. No. 11/456,845
→
METHOD OF MANUFACTURING NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM HAVING ETCHED DIFFERENTIAL HEIGHT LEAD STRUCTURES
App. No. 11/164,088
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PLANAR INTERCONNECTS
App. No. 11/162,629
→
INTEGRATED CIRCUIT PACKAGE SYSTEM USING INTERPOSER
App. No. 11/162,635
→