IP Library Granted Patent US 8,080,445
Granted Patent B1
US 8,080,445 · App. 12/876,425 · Granted Dec 20, 2011

Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers

Assignee: STATS ChipPAC, Ltd.
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Quick Facts
Patent No.
US 8,080,445
App. No.
12/876,425
Granted
Dec 20, 2011
Kind
B1
Abstract

A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.

Claims (47)

1. A method of making a semiconductor device, comprising:

providing a first substrate having a plurality of first conductive vias formed partially through the first substrate;

mounting a first semiconductor die over the first substrate electrically connected to the first conductive vias;

providing a second substrate having a plurality of second conductive vias formed partially through the second substrate;

forming an interconnect structure over the first substrate or second substrate;

depositing a penetrable encapsulant over the second substrate;

mounting the second substrate to the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant;

removing a portion of the first substrate to expose the first conductive vias;

removing a portion of the second substrate to expose the second conductive vias;

forming a redistribution layer over the first substrate electrically connected to the first conductive vias;

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first substrate, second substrate, and interconnect structure.

2. The method of claim 1 , further including mounting a second semiconductor die over the second substrate electrically connected to the second conductive vias.

3. The method of claim 1 , wherein the first substrate is electrically connected to the second substrate through the interconnect structure.

4. The method of claim 1 , wherein the penetrable encapsulant has thermally conductive properties.

5. A method of making a semiconductor device, comprising:

providing a first substrate having a plurality of first conductive vias formed in the first substrate;

mounting a first semiconductor die over the first substrate electrically connected to the first conductive vias;

providing a second substrate having a plurality of second conductive vias formed in the second substrate;

forming an interconnect structure over the first substrate or second substrate;

mounting the second substrate to the first substrate with a first encapsulant disposed between the first substrate and second substrate to embed the first semiconductor die and interconnect structure in the first encapsulant;

forming a first insulating layer over the first substrate and first conductive vias;

forming a first conductive layer over the first insulating layer;

forming a second insulating layer over the first insulating layer and first conductive layer;

forming a third insulating layer over the second substrate and second conductive vias;

forming a second conductive layer over the third insulating layer; and

forming a fourth insulating layer over the third insulating layer and second conductive layer.

6. The method of claim 5 , further including:

forming the first conductive vias partially through the first substrate;

removing a portion of the first substrate to expose the first conductive vias;

forming the second conductive vias partially through the second substrate; and

removing a portion of the second substrate to expose the second conductive vias.

7. The method of claim 5 , further including mounting a second semiconductor die over the second substrate electrically connected to the second conductive vias.

8. The method of claim 5 , further including forming a redistribution layer over the first substrate electrically connected to the first conductive vias.

9. The method of claim 5 , further including forming a plurality of third conductive vias through the first semiconductor die.

10. The method of claim 5 , further including depositing an underfill material under the first semiconductor die.

11. A method of making a semiconductor device, comprising:

providing a first through silicon via (TSV) interposer;

mounting a first semiconductor die over the first TSV interposer;

providing a second TSV interposer;

depositing an encapsulant over the second TSV interposer prior to mounting the second TSV interposer to the first TSV interposer;

mounting the second TSV interposer to the first TSV interposer and over the first semiconductor die with the encapsulant disposed between the first TSV interposer and second TSV interposer to embed the first semiconductor die in the encapsulant;

forming an interconnect structure over the first TSV interposer or second TSV interposer to electrically connect the first TSV interposer and second TSV interposer;

removing a portion of the first TSV interposer;

removing a portion of the second TSV interposer; and

mounting a second semiconductor die over the second TSV interposer.

12. The method of claim 11 , further including mounting a second semiconductor die over the first semiconductor die prior to mounting the second TSV interposer.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0272. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0730 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0272 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2010
From: PAGAILA, REZA A.
To: STATS CHIPPAC, LTD.
Reel/Frame 024945/0760 →