IP Library Granted Patent US 8,106,500
Granted Patent B2
US 8,106,500 · App. 12/777,023 · Granted Jan 31, 2012

Stackable integrated circuit package system

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Quick Facts
Patent No.
US 8,106,500
App. No.
12/777,023
Granted
Jan 31, 2012
Kind
B2
Abstract

A stackable integrated circuit package system includes: a substrate having a first side and a second side opposite the first side, the substrate having a cavity provided therein; a first integrated circuit die in the cavity with a first interconnect extending out from the cavity without connection and a second interconnect connected to the first side; a first mold compound to cover the first integrated circuit die, the second interconnect, and a portion of the first interconnect; a second integrated circuit die mounted to the first integrated circuit die with a third interconnect connected to the second side; a second mold compound to cover the second integrated circuit die and the third interconnect; and external interconnects, not encapsulated by the second encapsulant, mounted on the second side.

Claims (27)

1. A stackable integrated circuit package system comprising:

a substrate having a first side and a second side opposite the first side, the substrate having a cavity provided therein;

a first integrated circuit die in the cavity with a first interconnect extending out from the cavity without connection and a second interconnect connected to the first side;

a first mold compound to cover the first integrated circuit die, the second interconnect, and a portion of the first interconnect;

a second integrated circuit die mounted to the first integrated circuit die with a third interconnect connected to the second side;

a second mold compound to cover the second integrated circuit die and the third interconnect; and

external interconnects, not encapsulated by the second encapsulant, mounted on the second side.

2. The system as claimed in claim 1 wherein the first mold compound to cover the first side.

3. The system as claimed in claim 1 wherein the first mold compound is a center gate mold on the first side.

4. The system as claimed in claim 1 further comprising a third mold compound to surround the first mold compound with the interconnect exposed.

5. The system as claimed in claim 1 wherein the second integrated circuit die has the interconnect provided thereon and the second mold compound exposed the interconnect.

6. The system as claimed in claim 1 wherein:

the first integrated circuit die having the interconnect provided thereon in the substrate having the cavity is within the cavity;

the first mold compound to cover the first integrated circuit die, having the interconnect exposed, in the cavity fills the cavity;

the second integrated circuit die is mounted to a non-active side of the first integrated circuit die;

the second mold compound to cover the second integrated circuit die to the substrate is attached to the first mold compound; and

further comprising:

a first bond wire between the first integrated circuit die and a first side of the substrate; and

a second bond wire between the second integrated circuit die and a second side the substrate.

7. The system as claimed in claim 6 further comprising:

a top package having a top external interconnect; and

the top package on the stackable integrated circuit package system with the top external interconnect attached to the interconnect.

8. The system as claimed in claim 6 further comprising:

a top package having a top external interconnect; and

the top package on the stackable integrated circuit package system with the top external interconnect attached to the interconnect and the first side.

9. The system as claimed in claim 6 wherein the second mold compound is a center gate mold on the second side.

10. The system as claimed in claim 6 further comprising a hermetic seal formed with the first molding compound and the second molding compound.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0272. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0730 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0272 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →