Integrated circuit packaging system with a dual board-on-chip structure and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: providing a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity; mounting a second board-on-chip-structure over the first board-on-chip-structure, the second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity; connecting the first board-on-chip-structure to the second board-on-chip-structure with an internal interconnect; and encapsulating the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect with an encapsulation.
1. A method of manufacture of an integrated circuit packaging system comprising:
providing a first hoard-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity;
mounting a second board-on-chip-structure over the first board-on-chip-structure, the second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity and having a first trenched area adjacent to the cavity providing an electrical connection to a back side of a first functional side of the interposer;
connecting the first board-on-chip-structure to the second board-on-chip-structure with an internal interconnect; and
encapsulating the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect with an encapsulation.
2. The method as claimed in claim 1 further comprising:
connecting the first integrated circuit die to the substrate through the substrate cavity with the internal interconnects;
connecting the second integrated circuit die to the interposer through the interposer cavity with the internal interconnects; or
connecting a combination thereof.
3. The method as claimed in claim 1 wherein:
providing the first board-on-chip-structure includes providing a second trenched area around the substrate cavity.
4. The method as claimed in claim 1 wherein:
mounting the second board-on-chip-structure includes providing the first trenched area around the interposer cavity, around an edge of the interposer or a combination thereof.
5. The method as claimed in claim 1 further comprising:
connecting the first integrated circuit die to the substrate through the substrate cavity with the internal interconnects; and
forming a protrusion around the internal interconnects connecting the first integrated circuit die to the substrate.
6. A method of manufacture of an integrated circuit packaging system comprising:
providing a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity;
mounting a second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity and having a first trenched area adjacent to the cavity providing an electrical connection to a back side of a first functional side of the interposer;
connecting the first board-on-chip-structure to the second board-on-chip-structure with an internal interconnect;
forming terminal interconnects below the substrate, above the interposer, or a combination there of; and
encapsulating the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect with an encapsulation.
7. The method as claimed in claim 6 further comprising:
mounting an array package, a quad-flatpak-no-leads, a compound circuit, a passive component, an integrated circuit die, or a combination thereof.
8. The method as claimed in claim 6 wherein:
encapsulating the second board-on-chip-structure includes leaving a first functional side of the interposer exposed from a top surface of the encapsulation.
9. The method as claimed in claim 6 further comprising:
connecting a dual board-on-chip package above the second board-on-chip-structure.
10. The method as claimed in claim 6 wherein:
encapsulating includes partially encapsulating the terminal interconnects below the substrate, above the interposer, or a combination thereof with the encapsulation.
11. An integrated circuit packaging system comprising:
a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity;
a second board-on-chip-structure mounted over the first board-on-chip-structure, the second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity and having a first trenched area adjacent to the cavity providing an electrical connection to a back side of a first functional side of the interposer;
the first board-on-chip-structure connected to the second board-on-chip-structure with an internal interconnect; and
an encapsulation that encapsulates the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect.
12. The system as claimed in claim 11 wherein:
the first integrated circuit die is connected to the substrate through the substrate cavity with the internal interconnects;
the second integrated circuit die is connected to the interposer through the interposer cavity with the internal interconnects; or
a combination thereof.
13. The system as claimed in claim 11 wherein:
the first board-on-chip-structure includes a second trenched area around the substrate cavity.
14. The system as claimed in claim 11 wherein:
the second board-on-chip-structure includes the first trenched area around the interposer cavity, around an edge of the interposer or a combination thereof.
15. The system as claimed in claim 11 wherein:
the first integrated circuit die is connected to the substrate through the substrate cavity with the internal interconnects; and
further comprising:
a protrusion around the internal interconnects connecting the first integrated circuit die to the substrate.
16. The system as claimed in claim 11 further comprising:
terminal interconnects formed below the substrate, formed above the interposer, or a combination thereof.
17. The system as claimed in claim 16 further comprising:
an array package, a quad-flatpak-no-leads, a compound circuit, a passive component, an integrated circuit die, or a combination thereof mounted above the second board-on-chip-structure.
18. The system as claimed in claim 16 further comprising:
a first functional side of the interposer exposed from a top surface of the encapsulation.
19. The system as claimed in claim 16 further comprising:
a dual board-on-chip package connected above the second board-on-chip-structure.
20. The system as claimed in claim 16 wherein:
the terminal interconnects below the substrate, above the interposer, or a combination thereof are partially encapsulated with the encapsulation.