Integrated circuit packaging system with package-on-package and method of manufacture thereof

1. A method of manufacture of an integrated circuit packaging system comprising:

providing an encapsulation system having a mold chase with a buffer layer attached thereto;

forming a base integrated circuit package including:

providing a base substrate,

connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon,

mounting a base component over the base substrate,

forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system;

releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed; and

mounting a stack integrated circuit package over the base integrated circuit package having the exposed interconnect on the base substrate and adjacent the base component, the base component partially exposed from the base encapsulation.

2. The method as claimed in claim 1 wherein providing the encapsulation system having the buffer layer includes providing the encapsulation system having a soft material.

3. The method as claimed in claim 1 wherein connecting the exposed interconnect includes attaching the exposed interconnect on the base substrate and adjacent the base component, the base component partially exposed from the base encapsulation.

4. The method as claimed in claim 1 wherein forming the base integrated circuit package includes mounting an interface module over the base substrate, the interface module having the exposed interconnect attached thereon.

5. The method as claimed in claim 1 wherein mounting the base component includes mounting the base component over the base substrate, the base component having the exposed interconnect attached thereon.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing an encapsulation system having a mold chase with a buffer layer attached thereto;

forming a base integrated circuit package including:

providing a base substrate,

connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon and protected by the buffer layer,

mounting a base component over the base substrate,

forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system, the base encapsulation having a recess with characteristics of the buffer layer removed;

releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation in the recess, the exposed interconnect having characteristics of the buffer layer removed; and

mounting a stack integrated circuit package over the base integrated circuit package having the exposed interconnect on the base substrate and adjacent the base component, the base component partially exposed from the base encapsulation.

7. The method as claimed in claim 6 wherein providing the encapsulation system having the buffer layer includes providing a film.

8. The method as claimed in claim 6 further comprising mounting a stack integrated circuit package over the base integrated circuit package, the base integrated circuit package having an interface module over the base component and with the exposed interconnect attached thereon.

9. The method as claimed in claim 6 further comprising mounting a stack integrated circuit package over the base integrated circuit package, whereby the base integrated circuit package having the base component includes a redistribution layer die with the exposed interconnect attached thereon.

10. An integrated circuit packaging system comprising:

a base integrated circuit package including:

a base substrate,

an exposed interconnect connected to the base substrate,

a base component over the base substrate,

a base encapsulation, having characteristics of being formed by an encapsulation system with a mold chase and a buffer layer attached to the mold chase, the exposed interconnect having characteristics of the buffer layer removed and partially exposed from the base encapsulation, and

a stack integrated circuit package over the base integrated circuit package having the exposed interconnect on the base substrate and adjacent the base component, the base component partially exposed from the base encapsulation, and

wherein:

the exposed interconnect includes the exposed interconnect protected by the base encapsulation; and

the base encapsulation includes a recess in which a portion of the exposed interconnect is exposed, the recess having characteristics of the buffer layer removed.

11. The system as claimed in claim 10 wherein the base encapsulation having characteristics of being formed by the encapsulation system with the buffer layer includes the base encapsulation having characteristics of being formed by the encapsulation system with a soft material.

12. The system as claimed in claim 10 wherein the exposed interconnect includes the exposed interconnect on the base substrate and adjacent the base component, the base component partially exposed from the base encapsulation.

13. The system as claimed in claim 10 wherein the base integrated circuit package includes an interface module over the base substrate, the interface module having the exposed interconnect attached thereon.

14. The system as claimed in claim 10 wherein the base component includes the base component over the base substrate, the base component having the exposed interconnect attached thereto.

15. The system as claimed in claim 10 wherein the base encapsulation having characteristics of being formed by the encapsulation system with the buffer layer includes the encapsulation system with a film.

16. The system as claimed in claim 10 further comprising a stack integrated circuit package over the base integrated circuit package, the base integrated circuit package having an interface module over the base component and with the exposed interconnect attached thereon.

17. The system as claimed in claim 10 further comprising a stack integrated circuit package over the base integrated circuit package, whereby the base integrated circuit package having the base component includes a redistribution layer die with the exposed interconnect attached thereon.