IP Library › Assignment 052907/0650
Patent Assignment
Reel/Frame 052907/0650

RELEASE OF SECURITY INTEREST

Recorded: 2020-06-11 Received: 2020-06-11 Pages: 27
Assignor
Assignees
STATS CHIPPAC, INC.
46429 LANDING PARKWAY, FREMONT, CA, 94538, UNITED STATES
STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, 768442, SINGAPORE
Covered Applications (100)
ENCAPSULANT CAVITY INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF FABRICATION THEREOF
App. No. 12/892,907
→
INTEGRATED CIRCUIT PACKAGE SYSTEM USING HEAT SLUG
App. No. 12/880,415
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE FOR ENCAPSULATED DIE HAVING PRE-APPLIED PROTECTIVE LAYER
App. No. 12/822,080
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/792,629
→
GROOVING BUMPED WAFER PRE-UNDERFILL SYSTEM
App. No. 12/763,390
→
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING SHIELD
App. No. 12/762,602
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE
App. No. 12/759,158
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/722,759
→
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
App. No. 12/716,455
→
BONDING TOOL FOR MOUNTING SEMICONDUCTOR CHIPS
App. No. 12/635,536
→
SEMICONDUCTOR PACKAGE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO OPPOSITE SIDES OF TSV SUBSTRATE
App. No. 12/612,365
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORTED STACKED DIE
App. No. 12/565,698
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/560,312
→
SEMICONDUCTOR PACKAGE SYSTEM WITH SUBSTRATE HAVING DIFFERENT BONDABLE HEIGHTS AT LEAD FINGER TIPS
App. No. 12/547,439
→
SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURES
App. No. 12/540,174
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DAM MATERIAL AROUND PERIPHERY OF DIE TO REDUCE WARPAGE
App. No. 12/540,240
→
THROUGH-HOLE VIA ON SAW STREETS
App. No. 12/496,046
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/488,089
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/486,568
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS WITH TRENCH IN SAW STREET
App. No. 12/484,143
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/483,087
→
METHOD OF FORMING STRESS RELIEF LAYER BETWEEN DIE AND INTERCONNECT STRUCTURE
App. No. 12/481,404
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISOLATED PADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/474,757
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SLOTTED DIE PADDLE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/467,133
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AFTER ENCAPSULATION AND GROUNDED THROUGH INTERCONNECT STRUCTURE
App. No. 12/434,367
→
MULTIPACKAGE MODULE HAVING STACKED PACKAGES WITH ASYMMETRICALLY ARRANGED DIE AND MOLDING
App. No. 12/433,852
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND HEAT SPREADER WITH OPENINGS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/423,099
→
SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/423,320
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFINGER SUPPORT
App. No. 12/410,463
→
STACKED SEMICONDUCTOR PACKAGE ASSEMBLY HAVING HOLLOWED SUBSTRATE
App. No. 12/409,489
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THREE-DIMENSIONAL VERTICALLY ORIENTED INTEGRATED CAPACITORS
App. No. 12/404,134
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED DIE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/398,782
→
LEADFRAME DESIGN FOR QFN PACKAGE WITH TOP TERMINAL LEADS
App. No. 12/398,806
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SLUG
App. No. 12/398,163
→
PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/388,516
→
INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/331,347
→
SEMICONDUCTOR PACKAGE AND METHOD OF FORMING Z-DIRECTION CONDUCTIVE POSTS EMBEDDED IN STRUCTURALLY PROTECTIVE ENCAPSULANT
App. No. 12/329,458
→
LEADLESS INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 12/329,467
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF
App. No. 12/325,193
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING AN INTERNAL STRUCTURE PROTRUSION AND METHOD OF MANUFACTURE THEREOF
App. No. 12/273,540
→
BASE PACKAGE SYSTEM FOR INTEGRATED CIRCUIT PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/272,747
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INCREASED CONNECTIVITY AND METHOD OF MANUFACTURE THEREOF
App. No. 12/272,765
→
MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
App. No. 12/237,276
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ADHESIVE SEGMENT SPACER
App. No. 12/237,344
→
LEADLESS SEMICONDUCTOR CHIP CARRIER SYSTEM
App. No. 12/205,841
→
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY
App. No. 12/192,052
→
INTEGRATED CIRCUIT PACKAGE STACKING SYSTEM
App. No. 12/185,063
→
MULTI-LAYER PACKAGE-ON-PACKAGE SYSTEM
App. No. 12/185,067
→
A METHOD FOR FORMING AN ETCHED RECESS PACKAGE ON PACKAGE SYSTEM
App. No. 12/185,058
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ISOLATION BARRIER
App. No. 12/169,342
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONFORMAL SHIELDING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/146,124
→
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 12/146,135
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH TRIPLE FILM SPACER HAVING EMBEDDED FILLERS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/142,743
→
MOUNTABLE INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM
App. No. 12/136,768
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLEXIBLE SUBSTRATE AND MOUNDED PACKAGE
App. No. 12/136,007
→
METHOD AND APPARATUS FOR THERMALLY ENHANCED SEMICONDUCTOR PACKAGE
App. No. 12/135,830
→
SEMICONDUCTOR DEVICE AND METHOD OF CONFORMING CONDUCTIVE VIAS BETWEEN INSULATING LAYERS IN SAW STREETS
App. No. 12/121,682
→
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT
App. No. 12/121,752
→
INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
App. No. 12/114,744
→
INLINE INTEGRATED CIRCUIT SYSTEM
App. No. 12/101,915
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT STRUCTURE UNDER WIRE-IN-FILM ADHESIVE
App. No. 12/055,634
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT STRUCTURE FOR DIE OVERHANG
App. No. 12/051,267
→
SEMICONDUCTOR PACKAGE WITH PENETRABLE ENCAPSULANT JOINING SEMICONDUCTOR DIE AND METHOD THEREOF
App. No. 12/047,979
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKED DEVICES
App. No. 12/043,789
→
WAFER LEVEL DIE INTEGRATION AND METHOD THEREFOR
App. No. 12/042,026
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE ADHESIVE
App. No. 12/025,745
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERPOSER
App. No. 11/966,219
→
LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS
App. No. 11/964,567
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD LOCKING STRUCTURE
App. No. 11/964,501
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECT LOCK
App. No. 11/954,607
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL CONNECTIVITY
App. No. 11/936,532
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH UNDER PADDLE LEADFINGERS
App. No. 11/861,926
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DELAMINATION PREVENTION STRUCTURE
App. No. 11/857,206
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SIDE SUBSTRATE HAVING A TOP LAYER
App. No. 11/772,044
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERFERENCE-FIT FEATURE
App. No. 11/744,697
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONTOURED ENCAPSULATION
App. No. 11/735,397
→
STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RECESS
App. No. 11/618,807
→
WAFER LEVEL CHIP SCALE PACKAGE SYSTEM
App. No. 11/618,647
→
WAFER SYSTEM WITH PARTIAL CUTS
App. No. 11/615,929
→
INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/558,589
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD STRUCTURES INCLUDING A DUMMY TIE BAR
App. No. 11/558,387
→
BRIDGE STACK INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/555,682
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PAD TO PAD BONDING
App. No. 11/536,242
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERLOCK
App. No. 11/466,748
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LAMINATE BASE
App. No. 11/459,325
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CHANNEL
App. No. 11/380,652
→
WAFER SCALE HEAT SLUG SYSTEM
App. No. 11/379,011
→
MULTIPLE FLIP-CHIP INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/278,070
→
STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM WITH PASSIVE COMPONENTS
App. No. 11/276,682
→
NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE GROUND SITES
App. No. 11/276,684
→
INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
App. No. 11/276,646
→
INTEGRATED CIRCUIT PACKAGE IN PACKAGE SYSTEM
App. No. 11/276,647
→
WAFER LEVEL CHIP SCALE PACKAGE SYSTEM WITH A THERMAL DISSIPATION STRUCTURE
App. No. 11/276,611
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH A HEAT SINK
App. No. 11/307,532
→
INTEGRATED CIRCUIT PACKAGING SYSTEM INCLUDING A NON-LEADED PACKAGE
App. No. 11/307,383
→
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE
App. No. 11/164,336
→
THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS
App. No. 11/163,558
→
INTEGRATED CIRCUIT PROTRUDING PAD PACKAGE SYSTEM
App. No. 11/162,785
→
FLIP CHIP INTERCONNECTION STRUCTURE
App. No. 10/849,947
→
APPARATUS AND METHOD FOR THIN DIE DETACHMENT
App. No. 10/628,503
→