Integrated circuit packaging system having a cavity
View Patent ↗An integrated circuit packaging system includes: attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier bottom side; and forming a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation and with the carrier top side partially exposed with the cavity.
1. A method for manufacturing an integrated circuit packaging system comprising:
attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier top side with the interconnect having a height greater than a width; and
forming a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation and with the carrier top side partially exposed with the cavity.
2. The method as claimed in claim 1 further comprising mounting an integrated circuit within the cavity over the carrier top side.
3. The method as claimed in claim 1 further comprising:
mounting an integrated circuit within the cavity over the carrier; and
forming a second encapsulation over the integrated circuit with the cavity filled with the second encapsulation.
4. The method as claimed in claim 1 wherein forming the first encapsulation includes forming the first encapsulation along the periphery of the carrier.
5. The method as claimed in claim 1 further comprising:
mounting an integrated circuit package over the first encapsulation; and
connecting a package interconnect between the integrated circuit package and the interconnect.
6. A method for manufacturing an integrated circuit packaging system comprising:
attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier top side with the interconnect having a vertical configuration and a height greater than a width; and
forming a first encapsulation, having a cavity, around the interconnect over a periphery of the carrier top side with the interconnect partially exposed from the first encapsulation and with the carrier top side partially exposed with the cavity.
7. The method as claimed in claim 6 further comprising mounting an integrated circuit within the cavity over the carrier.
8. The method as claimed in claim 6 wherein attaching the carrier and the interconnect includes attaching a connection site along the carrier top side and the interconnect.
9. The method as claimed in claim 6 further comprising forming the interconnect includes forming a solder ball.
10. The method as claimed in claim 6 further comprising attaching an external interconnect to the carrier bottom side.