IP Library Granted Patent US 7,968,995
Granted Patent B2
US 7,968,995 · App. 12/483,087 · Granted Jun 28, 2011

Integrated circuit packaging system with package-on-package and method of manufacture thereof

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Quick Facts
Patent No.
US 7,968,995
App. No.
12/483,087
Granted
Jun 28, 2011
Kind
B2
Abstract

A method of manufacture an integrated circuit packaging system includes: providing a base substrate; mounting a first base integrated circuit over the base substrate; mounting a second base integrated circuit over the first base integrated circuit; attaching a stacking interconnect to the base substrate and adjacent to the first base integrated circuit; and forming a base encapsulation, having a recess portion from a corner of the base encapsulation and a step portion adjacent to the recess portion, with the step portion over the second base integrated circuit and the recess portion exposing the stacking interconnect.

Claims (46)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a base substrate;

mounting a first base integrated circuit over the base substrate;

mounting a second base integrated circuit over the first base integrated circuit;

attaching a stacking interconnect to the base substrate and adjacent to the first base integrated circuit; and

forming a base encapsulation, having a recess portion from a corner of the base encapsulation and a step portion adjacent to the recess portion, with the step portion over the second base integrated circuit and the recess portion exposing the stacking interconnect.

2. The method as claimed in claim 1 further comprising mounting a stack integrated circuit package over the recess portion and to connect to the stacking interconnect exposed at the recess portion.

3. The method as claimed in claim 1 wherein:

mounting the first base integrated circuit over the base substrate includes mounting a first base inactive side of the first base integrated circuit facing away from the base substrate; and

mounting the second base integrated circuit over the first base integrated circuit includes mounting a second base inactive side of the second base integrated circuit facing the first base integrated circuit.

4. The method as claimed in claim 1 wherein mounting the second base integrated circuit over the first base integrated circuit includes overhanging the second base integrated circuit over the first base integrated circuit.

5. The method as claimed in claim 1 wherein forming the base encapsulation, having the recess portion from the corner of the base encapsulation and the step portion adjacent to the recess portion, with the step portion over the second base integrated circuit and the recess portion exposing the stacking interconnect includes forming the recess portion at least partially over the first base integrated circuit.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a base substrate;

mounting a first base integrated circuit over the base substrate;

mounting a second base integrated circuit over the first base integrated circuit with the second base integrated circuit overhanging the first base integrated circuit;

attaching a stacking interconnect to the base substrate and adjacent to the first base integrated circuit;

forming a base encapsulation, having a recess portion from a corner of the base encapsulation and a step portion adjacent to the recess portion, with the step portion over the second base integrated circuit and the recess portion exposing the stacking interconnect; and

attaching an external interconnect below the base substrate.

7. The method as claimed in claim 6 wherein mounting the second base integrated circuit over the first base integrated circuit with the second base integrated circuit overhanging the first base integrated circuit includes mounting the second base integrated circuit at an opposite corner of the base substrate as the recess portion of the base encapsulation.

8. The method as claimed in claim 6 further comprising mounting a stack integrated circuit package having a stack substrate to the stacking interconnect.

9. The method as claimed in claim 6 further comprising mounting a stack integrated circuit package adjacent to the step portion.

10. The method as claimed in claim 6 wherein:

mounting the first base integrated circuit includes mounting a flip chip; and

mounting the second base integrated circuit includes mounting an integrated circuit die.

11. An integrated circuit packaging system comprising:

a base substrate;

a first base integrated circuit over the base substrate;

a second base integrated circuit over the first base integrated circuit;

a stacking interconnect attached to the base substrate and adjacent to the first base integrated circuit; and

a base encapsulation, having a recess portion from a corner of the base encapsulation and a step portion adjacent to the recess portion, with the step portion over the second base integrated circuit and the recess portion exposing the stacking interconnect.

12. The system as claimed in claim 11 further comprising a stack integrated circuit package over the recess portion and connected to the stacking interconnect exposed at the recess portion.

13. The system as claimed in claim 11 wherein:

the first base integrated circuit over the base substrate includes mounting a first base inactive side of the first base integrated circuit facing away from the base substrate; and

the second base integrated circuit over the first base integrated circuit includes mounting a second base inactive side of the second base integrated circuit facing the first base integrated circuit.

14. The system as claimed in claim 11 wherein the second base integrated circuit overhangs the first base integrated circuit.

15. The system as claimed in claim 11 wherein forming the base encapsulation includes the recess portion at least partially over the first base integrated circuit.

16. The system as claimed in claim 11 wherein:

the second base integrated circuit overhangs the first base integrated circuit; and further comprising:

an external interconnect under the base substrate.

17. The system as claimed in claim 16 wherein the second base integrated circuit is at an opposite corner of the base substrate as the recess portion.

18. The system as claimed in claim 16 further comprising a stack integrated circuit package having a stack substrate mounted to the stacking interconnect.

19. The system as claimed in claim 16 further comprising a stack integrated circuit package adjacent to the step portion.

20. The system as claimed in claim 16 wherein:

the first base integrated circuit includes a flip chip; and

the second base integrated circuit includes an integrated circuit die.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0301. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064913/0352 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052907/0650 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0301 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2009
From: KO, CHAN HOON; PARK, SOO-SAN; CHI, HEEJO
To: STATS CHIPPAC LTD.
Reel/Frame 022852/0706 →