Wafer level die integration and method therefor

1. A method of manufacturing a semiconductor device, comprising:

providing a wafer;

forming a first insulation layer over a top surface of the wafer;

forming a first interconnect structure over the first insulation layer with temperatures in excess of 200° C.;

forming a photoresist layer having an opening over the first interconnect structure;

forming a metal pillar in the opening in the photoresist layer and in electrical contact with the first interconnect structure;

mounting a semiconductor die to the first interconnect structure with an active surface of the semiconductor die facing the first interconnect structure;

forming encapsulant over the semiconductor die;

forming a second interconnect structure with temperatures below 200° C., the second interconnect structure including a first conductive layer formed over the encapsulant in electrical contact with the metal pillar and a second insulation layer formed over the first conductive layer; and

removing a portion of a backside of the wafer opposite the top surface of the wafer.

2. The method of claim 1 , including forming a thermal release layer over the wafer.

3. The method of claim 1 , including connecting backgrinding tape over the second interconnect structure.

4. The method of claim 1 , including bonding a permanent support substrate to the semiconductor device.

5. The method of claim 1 , wherein removing the portion of the backside of the wafer opposite the top surface of the wafer includes:

removing a first amount of the wafer using a grinding process; and

removing a second amount of the wafer using a wet etch, dry etch, or chemical-mechanical planarization process.

6. The method of claim 1 , including etching a via into the encapsulant to expose a portion of the metal pillar.

7. The method of claim 1 , including forming a buffer layer over the semiconductor die.

8. The method of claim 7 , including etching a via into the buffer layer to expose a portion of the metal pillar.

9. A method of manufacturing a semiconductor device, comprising:

providing a wafer;

forming a first interconnect structure over the wafer;

forming a raised metal layer over the first interconnect structure;

mounting a semiconductor die over the first interconnect structure with an active surface of the semiconductor die facing the first interconnect structure;

forming encapsulant over the semiconductor die;

forming a second interconnect structure with temperatures below 200° C., the second interconnect structure including a first conductive layer formed over the encapsulant in electrical contact with the raised metal layer and a first insulation layer formed over the first conductive layer; and

removing a portion of a backside of the wafer.

10. The method of claim 9 , including forming a thermal release layer over the wafer.

11. The method of claim 9 , including connecting backgrinding tape over the second interconnect structure.

12. The method of claim 9 , including bonding a permanent support substrate to the semiconductor device.

13. The method of claim 9 , wherein removing the portion of the backside of the wafer includes:

removing a first amount of the wafer using a grinding process; and

removing a second amount of the wafer using a wet etch, dry etch, or chemical-mechanical planarization process.

14. The method of claim 9 , including etching a via into the encapsulant to expose a portion of the raised metal layer.

15. The method of claim 9 , including forming a buffer layer over the semiconductor die.

16. The method of claim 15 , including etching a via into the buffer layer to expose a portion of the raised metal layer.

17. A method of manufacturing a semiconductor device, comprising:

providing a wafer;

forming a first insulation layer over a top surface of the wafer;

forming a first interconnect structure over the top surface of the wafer;

removing a portion of a backside of the wafer opposite the top surface of the wafer to expose a portion of the first insulation layer;

removing the portion of the first insulation layer to expose a portion of the first interconnect structure;

connecting a first semiconductor die to the exposed portion of the first interconnect structure; and

depositing a first encapsulant over the first semiconductor die.

18. The method of claim 17 , including:

forming a raised metal layer over the exposed portion of first interconnect structure;

mounting a second semiconductor die over the first interconnect structure;

forming a second encapsulant over the second semiconductor die; and

forming a second interconnect structure with temperatures below 200° C., including a first conductive layer formed over the second encapsulant in electrical contact with the raised metal layer and a second insulation layer formed over the first conductive layer.

19. The method of claim 17 , including forming a release layer over the wafer.

20. The method of claim 17 , wherein removing the portion of the backside of the wafer opposite the top surface of the wafer includes:

removing a first amount of the wafer using a grinding process; and

removing a second amount of the wafer using a wet etch, dry etch, or chemical-mechanical planarization process.

21. The method of claim 17 , including depositing a supporting substrate over the first encapsulant.