IP Library Granted Patent US 7,985,623
Granted Patent B2
US 7,985,623 · App. 11/735,397 · Granted Jul 26, 2011

Integrated circuit package system with contoured encapsulation

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Quick Facts
Patent No.
US 7,985,623
App. No.
11/735,397
Granted
Jul 26, 2011
Kind
B2
Abstract

An integrated circuit package system is provided including providing a carrier, mounting an integrated circuit die on the carrier, connecting the integrated circuit die with the carrier, and forming an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress.

Claims (42)

1. A method of manufacturing an integrated circuit package system comprising:

providing a carrier;

mounting an integrated circuit die on a top side of the carrier;

connecting the integrated circuit die with the carrier;

forming an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress, wherein forming the encapsulation having the multi-sloped side includes forming a sidewall having a circular configuration with a radius greater than 0.125 mm; and

forming a first external interconnect on the top side of the carrier adjacent to and separated from the encapsulation including forming a second external interconnect on a bottom side of the carrier opposite the first external interconnect.

2. The method as claimed in claim 1 wherein forming the encapsulation having the multi-sloped side includes forming an S-shaped side.

3. The method as claimed in claim 1 further comprising mounting a stacking integrated circuit package over the carrier and the encapsulation.

4. The method as claimed in claim 1 wherein:

connecting the integrated circuit die with the carrier includes:

connecting a bond wire between the integrated circuit die and the carrier; and

forming the encapsulation having the multi-sloped side further includes:

forming the encapsulation to substantially conform to the bond wire.

5. A method of manufacturing an integrated circuit package system comprising:

providing a carrier;

mounting an integrated circuit die on a top side of the carrier;

connecting a bond wire between the integrated circuit die with the carrier;

forming an encapsulation having a multi-sloped side, over the integrated circuit die, to substantially conform to the bond wire for reducing ejection stress, wherein forming the encapsulation having the multi-sloped side includes forming a sidewall having a circular configuration with a radius greater than 0.125 mm; and

forming a first external interconnect on the top side of the carrier adjacent to and separated from the encapsulation including forming a second external interconnect on a bottom side of the carrier opposite the first external interconnect in which the first external interconnect may be formed in multiple rows.

6. The method as claimed in claim 5 wherein forming the encapsulation having the multi-sloped side includes:

forming a first region having a first thickness that is horizontal and adjacent to the multi-sloped side; and

forming a second region having a second thickness of the multi-sloped side with the second thickness is twenty percent less than first thickness.

7. The method as claimed in claim 5 wherein providing the carrier includes providing a substrate.

8. The method as claimed in claim 5 further comprising mounting a stacking integrated circuit package over the carrier and the encapsulation including attaching a bottom external interconnect to the first external interconnect.

9. The method as claimed in claim 5 further comprising attaching an external interconnect with the carrier at an opposing side of the encapsulation.

10. An integrated circuit package system comprising:

a carrier;

an integrated circuit die on a top side of the carrier;

an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress, wherein the encapsulation having the multi-sloped side includes forming a sidewall having a circular configuration with a radius greater than 0.125 mm; and

a first external interconnect formed on the top side of the carrier adjacent to and separated from the encapsulation includes a second external interconnect formed on a bottom side of the carrier opposite the first external interconnect.

11. The system as claimed in claim 10 wherein the encapsulation having the multi-sloped side includes an S-shaped side.

12. The system as claimed in claim 10 further comprising a stacking integrated circuit package over the carrier and the encapsulation.

13. The system as claimed in claim 10 further comprising a bond wire between the integrated circuit die and the carrier.

14. The system as claimed in claim 10 further comprising:

a bond wire between the integrated circuit die and the carrier; and wherein:

the encapsulation substantially conforms to the bond wire and the integrated circuit die.

15. The system as claimed in claim 14 wherein the encapsulation having the multi-sloped side includes:

a first region having a first thickness that is horizontal and adjacent to the multi-sloped side; and

a second region having a second thickness of the multi-sloped side with the second thickness is twenty percent less than first thickness.

16. The system as claimed in claim 14 wherein the carrier includes a substrate.

17. The system as claimed in claim 14 further comprising a stacking integrated circuit package over the carrier and the encapsulation includes a bottom external interconnect attached to the first external interconnect.

18. The system as claimed in claim 14 further comprising an external interconnect attached with the carrier at an opposing side of the encapsulation.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0301. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064913/0352 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052907/0650 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0301 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2007
From: YIM, CHOONG BIN; KIM, YOUNG CHEOL
To: STATS CHIPPAC LTD.
Reel/Frame 019160/0193 →