IP Library Granted Patent US 8,004,073
Granted Patent B2
US 8,004,073 · App. 12/486,568 · Granted Aug 23, 2011

Integrated circuit packaging system with interposer and method of manufacture thereof

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Quick Facts
Patent No.
US 8,004,073
App. No.
12/486,568
Granted
Aug 23, 2011
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: attaching a lower integrated circuit, having a first through via, over a substrate with the first through via coupled to the substrate; mounting a pre-formed interposer, having an interposer through via and an integrated passive device, over the lower integrated circuit with the interposer through via coupled to the first through via; attaching an upper integrated circuit, having a second through via, over the pre-formed interposer; and forming an encapsulation over the upper integrated circuit and the pre-formed interposer.

Claims (44)

1. A method of manufacture of an integrated circuit packaging system comprising:

attaching a lower integrated circuit, having a first through via, over a substrate with the first through via coupled to the substrate;

mounting a pre-formed interposer, having an interposer through via and an integrated passive device, over the lower integrated circuit with the interposer through via coupled to the first through via;

connecting a first electrical interconnect between different types of integrated passive devices to form filtering circuits to form filtering circuits, attaching an upper integrated circuit, having a second through via, over the pre- formed interposer; and

forming an encapsulation over the upper integrated circuit and the pre-formed interposer.

2. The method as claimed in claim 1 further comprising connecting a first electrical interconnect between the integrated passive device and the interposer through via.

3. The method as claimed in claim 1 wherein mounting the pre- formed interposer over the lower integrated circuit includes mounting an embedded integrated circuit over the lower integrated circuit with the embedded integrated circuit within the pre-formed interposer.

4. The method as claimed in claim 1 further comprising connecting a second electrical interconnect between different portions of the substrate.

5. A method of manufacture of an integrated circuit packaging system comprising:

attaching a lower integrated circuit, having a first through via, over a substrate with the first through via coupled to the substrate;

mounting a pre-formed interposer, having an interposer through via, an integrated passive device, and a first electrical interconnect, over the lower integrated circuit with the interposer through via coupled to the first through via and the first electrical interconnect connected to the integrated passive device;

attaching an upper integrated circuit, having a second through via, over the pre- formed interposer, includes attaching a flip chip;

forming an encapsulation over the upper integrated circuit and the pre-formed interposer; and

attaching an external interconnect under the substrate.

6. The method as claimed in claim 5 wherein attaching the upper integrated circuit, having the second through via, over the pre-formed interposer includes connecting the second through via and the interposer through via.

7. The method as claimed in claim 5 wherein mounting the pre- formed interposer over the lower integrated circuit includes:

mounting a silicon interposer.

8. The method as claimed in claim 5 wherein:

mounting the pre-formed interposer over the lower integrated circuit includes:

mounting an embedded integrated circuit over the lower integrated circuit with the embedded integrated circuit within the pre-formed interposer; and

attaching the upper integrated circuit, having the second through via, over the pre- formed interposer includes:

mounting the upper integrated circuit over the embedded integrated circuit.

9. An integrated circuit packaging system comprising:

a substrate;

a lower integrated circuit, having a first through via, over the substrate with the first through via coupled to the substrate;

a pre-formed interposer, having an interposer through via and an integrated passive device, over the lower integrated circuit with the interposer through via coupled to the first through via;

an upper integrated circuit, having a second through via, over the pre-formed interposer; and

an encapsulation over the upper integrated circuit and the pre-formed interposer.

10. The system as claimed in claim 9 further comprising a first electrical interconnect between the integrated passive device and the interposer through via.

11. The system as claimed in claim 9 wherein the pre-formed interposer includes an embedded integrated circuit over the lower integrated circuit.

12. The system as claimed in claim 9 further comprising a first electrical interconnect between different types of the integrated passive devices to form filtering circuits.

13. The system as claimed in claim 9 further comprising a second electrical interconnect between different portions of the substrate.

14. The system as claimed in claim 9 wherein:

the pre-formed interposer includes a first electrical interconnect connected to the integrated passive device; and

further comprising:

an external interconnect under the substrate.

15. The system as claimed in claim 14 wherein the upper integrated circuit having the second through via includes the second through via connected to the interposer through via.

16. The system as claimed in claim 14 wherein the pre-formed interposer includes a silicon interposer.

17. The system as claimed in claim 14 wherein:

the pre-formed interposer includes:

an embedded integrated circuit over the lower integrated circuit; and

the upper integrated circuit, having the second through via, over the pre-formed interposer includes:

the upper integrated circuit over the embedded integrated circuit.

18. The system as claimed in claim 14 wherein the upper integrated circuit includes a flip chip.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0301. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064913/0352 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052907/0650 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0301 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2009
From: KO, CHAN HOON; PARK, SOO-SAN
To: STATS CHIPPAC LTD.
Reel/Frame 022931/0253 →