IP Library Granted Patent US 8,080,446
Granted Patent B2
US 8,080,446 · App. 12/473,253 · Granted Dec 20, 2011

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,080,446
App. No.
12/473,253
Granted
Dec 20, 2011
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; and forming an encapsulation that encapsulates the integrated circuit, the routing structure.

Claims (61)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing an integrated circuit;

applying a wire-in-film adhesive over the integrated circuit;

mounting a routing structure having a first functional side and a second functional side above the integrated circuit, with the routing structure having an overhang over the integrated circuit;

mounting a vertical interconnect to the functional side of the routing structure and over the overhang, and the vertical interconnect extending vertically away from the routing structure; and

forming an encapsulation as a single piece in direct contact with the first functional side, the second functional side, the wire-in-film adhesive, and sides of the vertical interconnect above the routing structure.

2. The method as claimed in claim 1 further comprising:

mounting a substrate below the integrated circuit; and

connecting the integrated circuit to the substrate with internal interconnects.

3. The method as claimed in claim 1 further comprising:

mounting a substrate below the integrated circuit; and

connecting the routing structure to the substrate with z-interconnects.

4. The method as claimed in claim 1 further comprising:

connecting an external-package to the vertical interconnect.

5. The method as claimed in claim 1 wherein:

mounting the vertical interconnect includes mounting vertical interconnects in two rows.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing an integrated circuit;

applying a wire-in-film adhesive over the integrated circuit;

mounting a routing structure having a first functional side and a second functional side above the integrated circuit, with the routing structure having an overhang over the integrated circuit;

mounting a vertical interconnect to the functional side of the routing structure and over the overhang, and the vertical interconnect extending vertically away from the routing structure;

forming an encapsulation with mold risers and as a single piece wherein in direct contact with the first functional side, the second functional side, the wire-in-film adhesive, and sides of the vertical interconnect above the routing; and

connecting an external-package to a surface exposed from the encapsulation between the mold risers.

7. The method as claimed in claim 6 wherein:

mounting the integrated circuit includes mounting a wire-bonded die, a flip-chip, or a combination thereof; and

connecting the external-package to the surface exposed from the encapsulation includes connecting a flip-chip, an integrated circuit component package, or a combination thereof.

8. The method as claimed in claim 6 wherein:

forming the mold risers includes forming mold risers sufficiently high to provide structural support for the vertical interconnect and to provide a standoff height above the external package.

9. The method as claimed in claim 6 wherein:

forming the encapsulation encapsulating the vertical interconnect includes forming the encapsulation around a vertical interconnect, forming a hole in the encapsulation and filling the hole with the vertical interconnect, or a combination thereof.

10. The method as claimed in claim 6 wherein:

mounting the vertical interconnect includes mounting the vertical interconnects along two edges of the routing structure.

11. An integrated circuit packaging system comprising:

an integrated circuit;

a wire-in-film adhesive applied over the integrated circuit;

a routing structure having a first functional side and a second functional side mounted above the integrated circuit, with the routing structure having an overhang over the integrated circuit;

a vertical interconnect mounted to the functional side of the routing structure and over the overhang, and the vertical interconnect extends vertically away from the routing structure; and

an encapsulation formed as a single piece, in direct contact with the first functional side, the second functional side, the wire-in-film adhesive and sides of the vertical interconnect.

12. The system as claimed in claim 11 further comprising:

a substrate below the integrated circuit; and

the integrated circuit is connected to the substrate with internal interconnects.

13. The system as claimed in claim 11 further comprising:

a substrate below the integrated circuit; and

the routing structure is connected to the substrate with z-interconnects.

14. The system as claimed in claim 11 further comprising:

an external-package connected to the vertical interconnect.

15. The system as claimed in claim 11 wherein:

the vertical interconnects are mounted in two rows.

16. The system as claimed in claim 11 wherein:

the encapsulation includes mold risers rising vertically away from the routing structure; and

further comprising:

an external-package connected to a surface exposed from the encapsulation between the mold risers.

17. The system as claimed in claim 16 wherein:

the integrated circuit is a wire-bonded die, a flip-chip, or a combination thereof; and

the external-package is a flip-chip, an integrated circuit component package, or a combination thereof.

18. The system as claimed in claim 16 wherein:

the mold risers are sufficiently high to provide structural support for the vertical interconnect and to provide a standoff height above the external package.

19. The system as claimed in claim 16 wherein:

the vertical interconnect is an embedded-conductive-fillings formed in a hole of the encapsulation, an embedded solder ball or a combination thereof.

20. The system as claimed in claim 16 wherein:

the vertical interconnects are along two edges of the routing structure.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0272. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0730 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0272 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2009
From: CHOI, A LEAM; LEE, KENNY; YOON, IN SANG; SHIN, HANGIL
To: STATS CHIPPAC LTD.
Reel/Frame 022850/0609 →