IP Library Granted Patent US 8,049,322
Granted Patent B2
US 8,049,322 · App. 12/772,128 · Granted Nov 1, 2011

Integrated circuit package-in-package system and method for making thereof

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Quick Facts
Patent No.
US 8,049,322
App. No.
12/772,128
Granted
Nov 1, 2011
Kind
B2
Abstract

A method for making an integrated circuit package-in-package system includes: forming a first integrated circuit package including a first device and a first substrate and having a first interface; stacking a second integrated circuit package including a second device and a second substrate and having a second interface above the first integrated circuit package; and fitting the first interface directly on the second interface.

Claims (87)

1. A method for making an integrated circuit package-in-package system comprising:

forming a first integrated circuit package including a first device and a first substrate and having a first interface;

stacking a second integrated circuit package including a second device and a second substrate and having a second interface above the first integrated circuit package; and

fitting the first interface directly on the second interface with the first substrate located non-planar to the second substrate.

2. The method as claimed in claim 1 wherein:

forming the first integrated circuit package having the first interface comprises:

forming the first interface defined by a first electrical interface pattern on the first substrate of the first integrated circuit package;

stacking the second integrated circuit package having the second interface further comprises:

forming the second interface defined by a second electrical interface pattern on the second substrate of the second integrated circuit package;

fitting the first interface and the second interface further comprises:

mating the first electrical interface pattern and the second electrical interface pattern; and

further comprising:

stacking a third integrated circuit package having a third electrical interface pattern on the second integrated circuit package;

stacking a fourth integrated circuit package having a fourth electrical interface pattern on the third integrated circuit package;

mating the third electrical interface pattern and the fourth electrical interface pattern; and

encapsulating the first integrated circuit package, the second integrated circuit package, the third integrated circuit package, and the fourth integrated circuit package.

3. The method as claimed in claim 1 wherein:

forming the first integrated circuit package having the first interface comprises:

forming the first interface defined by a first electrical interface pattern on the first substrate of the first integrated circuit package;

stacking the second integrated circuit package having the second interface further comprises:

forming the second interface defined by a second electrical interface pattern on the second substrate of the second integrated circuit package;

fitting the first interface and the second interface further comprises:

mating the first electrical interface pattern and the second electrical interface pattern; and

further comprising:

stacking a third integrated circuit package having a third electrical interface pattern on the second integrated circuit package;

forming an encapsulation to cover the first integrated circuit package, the second integrated circuit package, and the third integrated circuit package;

forming a recess in the encapsulation to expose the third electrical interface pattern on a third substrate of the third integrated circuit package;

stacking a fourth integrated circuit package having a fourth electrical interface pattern in the recess on the third integrated circuit package; and

mating a portion of the third electrical interface pattern and the fourth electrical interface pattern.

4. A method for making an integrated circuit package-in-package system comprising:

forming a first integrated circuit package including a first device and a first substrate and having a first interface;

stacking a second integrated circuit package including a second device and a second substrate and having a second interface above the first integrated circuit package;

fitting the first interface directly on the second interface;

electrically connecting the first integrated circuit package and the second integrated circuit package; and

attaching a third integrated circuit package on the second integrated circuit package.

5. The method as claimed in claim 4 wherein attaching the third integrated circuit package on the second integrated circuit package includes electrically connecting the third integrated circuit package and the second integrated circuit package.

6. The method as claimed in claim 4 further comprising electrically connecting the first integrated circuit package and a package substrate.

7. An integrated circuit package-in-package system comprising:

a first integrated circuit including a first device and a first substrate and having a first interface;

a second integrated circuit including a second device and a second substrate and having a second interface above the first integrated circuit package; and

the first interface fitted directly on the second interface with the first substrate located non-planar to the second substrate.

8. The system as claimed in claim 7 wherein:

the first integrated circuit package having the first interface comprises:

the first interface defined by a first electrical interface pattern on the first substrate of the first integrated circuit package;

the second integrated circuit package having the second interface further comprises:

the second interface defined by a second electrical interface pattern on the second substrate of the second integrated circuit package;

the first interface fitted with the second interface further comprises:

the first electrical interface pattern mated with the second electrical interface pattern; and

further comprising:

a third integrated circuit package having a third electrical interface pattern on the second integrated circuit package;

a fourth integrated circuit package having a fourth electrical interface pattern on the third integrated circuit package;

the third electrical interface pattern mated with the fourth electrical interface pattern; and

an encapsulation to cover the first integrated circuit package, the second integrated circuit package, the third integrated circuit package, and the fourth integrated circuit package.

9. The system as claimed in claim 7 wherein:

the first integrated circuit package having the first interface comprises:

the first interface defined by a first electrical interface pattern on the first substrate of the first integrated circuit package;

the second integrated circuit package having the second interface further comprises:

the second interface defined by a second electrical interface pattern on the second substrate of the second integrated circuit package;

the first interface fitted with the second interface further comprises:

the first electrical interface pattern mated with the second electrical interface pattern; and

further comprising:

a third integrated circuit package having a third electrical interface pattern on the second integrated circuit package;

an encapsulation to cover the first integrated circuit package, the second integrated circuit package, and the third integrated circuit package,

a recess in the encapsulation to expose the third electrical interface pattern on a third substrate of the third integrated circuit package,

a fourth integrated circuit package having a fourth electrical interface pattern in the recess on the third integrated circuit package, and

a portion of the third electrical interface pattern mated with the fourth electrical interface pattern.

10. The system as claimed in claim 7 wherein:

the first integrated circuit package having the first interface has a first integrated circuit die;

the second integrated circuit package having the second interface above the first integrated circuit package has a second integrated circuit die;

the first interface fitted with the second interface is a compatible interface; and

the first integrated circuit package electrically connected to the second integrated circuit package; and

further comprising:

a third integrated circuit package on the second integrated circuit package has a third integrated circuit die.

11. The system as claimed in claim 10 wherein:

the first integrated circuit package having the first interface comprises:

the first interface defined by a first electrical interface pattern on the first substrate of the first integrated circuit package; and

the second integrated circuit package having the second interface above the first integrated circuit package further comprises:

the second integrated circuit package with a second integrated circuit die having a second electrical interface pattern, and

the second interface defined by the second electrical interface pattern; and

further comprising:

an encapsulation to cover the first integrated circuit package, the second integrated circuit package, and the third integrated circuit package;

a recess in the encapsulation to expose the third electrical interface pattern on a third substrate of the third integrated circuit package;

a fourth integrated circuit package having a fourth electrical interface pattern in the recess on the third integrated circuit package; and

a portion of the third electrical interface pattern mated with the fourth electrical interface pattern.

12. The system as claimed in claim 10 wherein the third integrated circuit package on the second integrated circuit package includes an interconnect between the third integrated circuit package and the second integrated circuit package.

13. The system as claimed in claim 10 further comprising the first integrated circuit package on a package substrate.

14. The system as claimed in claim 10 further comprising an interconnect between the first integrated circuit package and a package substrate.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0272. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0730 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0272 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →