Integrated circuit package system including wafer level spacer
View Patent ↗An integrated circuit package system that includes providing a wafer level spacer including apertures, which define unit spacers that are interconnected, and configuring the unit spacers to substantially align over devices formed within a substrate.
1. A method of manufacture of an integrated circuit package system comprising:
providing a wafer level spacer that includes a notch for orientation and apertures, which define unit spacers joined together by material of the wafer level spacer;
configuring the unit spacers to substantially align over semiconductor chips formed within a substrate; and
dicing to form a common vertical boundary shared by the unit spacers and the devices, semiconductor chips.
2. The method as claimed in claim 1 further comprising:
forming the apertures to include shapes selected from circles, ellipses, rectangles, squares, or poly-sided openings.
3. The method as claimed in claim 1 further comprising:
forming the apertures to align with scribe lines formed on the substrate.
4. The method as claimed in claim 1 further comprising:
attaching each of the unit spacers to the substrate in a single step.
5. The method as claimed in claim 1 wherein:
providing the wafer level spacer includes a wafer selected from material that prevents warpage failure, enhances thermal dissipation, or blocks electromagnetic radiation.
6. A method of manufacture of an integrated circuit package system comprising:
providing a wafer level spacer including apertures that define unit spacers joined together by material of the wafer level spacer;
aligning the wafer level spacer via a notch for orientation over a substrate with semiconductor chips;
dicing the wafer level spacer and the substrate to form a common vertical boundary shared by one of the unit spacers and one of the semiconductor chips; and
forming one of the unit spacers over one of the semiconductor chips.
7. The method as claimed in claim 6 wherein:
aligning the wafer level spacer over the substrate forms the unit spacers over each of the semiconductor chips in a single step.
8. The method as claimed in claim 6 further comprising:
selecting the semiconductor chips from active components, passive components, or a combination thereof.
9. The method as claimed in claim 6 further comprising:
stacking a spacer-less device over one of the semiconductor chips.
10. The method as claimed in claim 6 further comprising:
stacking a device over one of the semiconductor chips.
11. An integrated circuit package system comprising:
a semiconductor chip having the characteristics of being singulated from a substrate;
a unit spacer over the semiconductor chip sharing a common vertical boundary with the semiconductor chip, the unit spacer having the characteristics of being singulated from a wafer level spacer including a notch for orientation; and
apertures formed along the perimeter of the unit spacer.
12. The system as claimed in claim 11 wherein:
the apertures include shapes selected from circles, ellipses, rectangles, squares, or poly-sided openings.
13. The system as claimed in claim 11 wherein:
the apertures align with scribe lines formed on the substrate.
14. The system as claimed in claim 11 wherein:
the wafer level spacer includes a punch hole.
15. The system as claimed in claim 11 wherein:
the wafer level spacer includes a wafer selected from material that prevents warpage failure, enhances thermal dissipation, or blocks electromagnetic radiation.
16. The system as claimed in claim 11 wherein:
the semiconductor chip includes wire bond die, flip-chip die, stacked die, modular die, ASIC die, passive devices or a combination thereof.
17. The system as claimed in claim 11 wherein:
the semiconductor chip is attached to a structure.
18. The system as claimed in claim 11 further comprising:
a spacer-less device over the semiconductor chip.
19. The system as claimed in claim 11 further comprising:
a device over the semiconductor chip.