Integrated circuit package system for package stacking and manufacturing method thereof

1. A method of manufacturing a stackable multi-chip package system comprising:

forming external interconnects each having a base and a tip;

connecting a first integrated circuit die and the base;

stacking a second integrated circuit die over the first integrated circuit die in an active side to active side configuration including positioning a second external interconnect having a second base coplanar with the tip;

connecting the second integrated circuit die and the second base; and

molding an encapsulation on the first integrated circuit die, the second integrated circuit die, and the external interconnects partially exposed including each having the base and the tip coplanar with the encapsulation.

2. The method as claimed in claim 1 wherein stacking the second integrated circuit die over the first integrated circuit die includes placing an inter-chip structure in between.

3. The method as claimed in claim 1 further comprising stacking a first stackable multi-chip package system over a second stackable multi-chip package system.

4. The method as claimed in claim 1 further comprising:

mounting a first stackable multi-chip package system over a substrate;

stacking a second stackable multi-chip package system over the first stackable multi-chip package system; and

molding the first stackable multi-chip package system and the second stackable multi-chip package system with the substrate.

5. The method as claimed in claim 1 wherein:

connecting the first integrated circuit die and the base includes:

connecting the first integrated circuit die and an inner portion of the base; and

connecting the second integrated circuit die and the second base further includes:

connecting the second integrated circuit die and an inner portion of the second base.

6. A stackable multi-chip package system comprising:

external interconnects each having a base and a tip;

an interconnect between a first integrated circuit die and the base;

a second integrated circuit die over the first integrated circuit die in an active side to active side configuration includes a second external interconnect with a second base positioned coplanar with the tip;

a second internal interconnect between the second integrated circuit die and the second base; and

an encapsulation to partially cover the first integrated circuit die, the second integrated circuit die, and the external interconnects each includes the base and the tip coplanar with the encapsulation.

7. The system as claimed in claim 6 wherein the second integrated circuit die over the first integrated circuit die has an inter-chip structure in between.

8. The system as claimed in claim 6 further comprising a first stackable multi-chip package system over a second stackable multi-chip package system.

9. The system as claimed in claim 6 further comprising:

a first stackable multi-chip package system over a substrate;

a second stackable multi-chip package system over the first stackable multi-chip package system; and

a package encapsulation to cover the first stackable multi-chip package system and the second stackable multi-chip package system with the substrate.

10. The system as claimed in claim 6 wherein:

the interconnect between the first integrated circuit die and the base includes:

the interconnect between the first integrated circuit die and an inner portion of the base; and

the second internal interconnect between the second integrated circuit die and the base further includes:

the second internal interconnect between the second integrated circuit die and an inner portion of the base.

11. The system as claimed in claim 6 wherein:

the external interconnect is a L-shape external interconnect having the base and the tip;

the interconnect between the first integrated circuit die and the base is to an inner portion of the base;

the second integrated circuit die is offset over the first integrated circuit die in the active side to active side configuration;

the interconnect between the second integrated circuit die and the second base is to the inner portion of the second base; and

the encapsulation to partially cover the first integrated circuit die, the second integrated circuit die, and the external interconnect exposes a portion of the L-shape external interconnect, a first non-active side, and a second non-active side; and

further comprising:

a first active side of the first integrated circuit die; and

a second active side of the second integrated circuit die.

12. The system as claimed in claim 11 wherein the encapsulation includes:

a first land exposed; and

a second land exposed.

13. The system as claimed in claim 11 wherein the second integrated circuit die over the first integrated circuit die, in the offset and active side to active side configuration, has the second active side facing the first active side.

14. The system as claimed in claim 11 further comprising dual rows of lands with bases and tips exposed in alternating positions.

15. The system as claimed in claim 11 wherein the second integrated circuit die over the first integrated circuit die has the encapsulation in between for planar rigidity.