Integrated circuit packaging system with interposer and method of manufacture thereof
View Patent ↗A method of manufacture of an integrated circuit packaging system includes: providing an interposer having device contacts, interconnect contacts, and test pads including the interconnect contacts along an interconnect perimeter region of the interposer, the device contacts at a device perimeter region of the interposer with the device perimeter region within the interior of the interconnect perimeter region, and the test pads at a test perimeter region of the interposer with the test perimeter region encompassing the device perimeter region; and mounting an integrated circuit over the device contacts.
1. A method of manufacturing for an integrated circuit packaging system comprising:
providing an interposer having device contacts, interconnect contacts, and test pads including:
the interconnect contacts along an interconnect perimeter region of the interposer,
the device contacts at a device perimeter region of the interposer with the device perimeter region within the interior of the interconnect perimeter region, and
the test pads at a test perimeter region of the interposer with the test perimeter region encompassing the device perimeter region;
mounting an integrated circuit over the device contacts; and
providing terminal embedded interconnects, having a first region and a second region, connecting the interconnect contacts and the device contacts;
providing the first region having a first density of the terminal embedded interconnects; and
providing the second region having a second density of the terminal embedded interconnects with the first density greater than the second density and the terminal embedded interconnects in the second region connected to the device contacts.
2. The method as claimed in claim 1 wherein providing the interposer includes:
providing an equal number of interconnect sites, device sites, and test sites for the interconnect contacts, the device contacts and the test pads, respectively; and
providing at least a portion of the interconnect sites, the device sites, and the test sites populated with the interconnect contacts, the device contacts and the test pads, respectively.
3. The method as claimed in claim 1 wherein providing the interposer having the device contacts, the interconnect contacts, and the test pads includes providing test embedded interconnects between the device contacts and the test pads with the test embedded interconnects fanning out from the device perimeter region to the test perimeter region.
4. The method as claimed in claim 1 wherein providing the interposer includes the interconnect contacts, the device contacts, and the test pads exposed on a first side.
5. An integrated circuit packaging system comprising:
an interposer having device contacts, interconnect contacts, and test pads including:
the interconnect contacts along an interconnect perimeter region of the interposer,
the device contacts at a device perimeter region of the interposer with the device perimeter region within the interior of the interconnect perimeter region, and
the test pads at a test perimeter region of the interposer with the test perimeter region encompassing the device perimeter region;
an integrated circuit over the device contacts; and
wherein the interposer having the device contacts, the interconnect contacts, and the test pads includes:
terminal embedded interconnects, having a first region and a second region, connected between the interconnect contacts and the device contacts;
the first region having a first density of the terminal embedded interconnects; and
the second region having a second density of the terminal embedded interconnects with the first density greater than the second density and the second region is connected to the rows of device contacts.
6. The system as claimed in claim 5 wherein the interposer includes:
an equal number of interconnect sites, device sites, and test sites for the interconnect contacts, the device contacts and the test pads, respectively; and
at least a portion of the interconnect sites, the device sites, and the test sites are populated with the interconnect contacts, the device contacts and the test pads, respectively.
7. The system as claimed in claim 5 wherein the interposer having the device contacts, the interconnect contacts, and the test pads includes test embedded interconnects between the device contacts and the test pads with the test embedded interconnects fanning out from the device perimeter region to the test perimeter region.
8. The system as claimed in claim 5 wherein the interposer includes the interconnect pads, the device contacts and the test pads exposed on a first side.
9. The system as claimed in claim 5 wherein:
the device perimeter region includes rows of device contacts; and
the test perimeter region includes rows of test pads.
10. The system as claimed in claim 9 further comprising a covering structure over the integrated circuit with the interconnect contacts and the test pads exposed.
11. The system as claimed in claim 9 further comprising:
an encapsulation over the integrated circuit; and
a conductive structure over or exposed from the encapsulation.
12. The system as claimed in claim 9 further comprising:
a carrier;
an integrated circuit device over the carrier;
a package encapsulation over the carrier covering at least a portion of the integrated circuit, the interposer, and the integrated circuit device; and wherein:
the interposer is over the integrated circuit device; and
the interconnect contacts are connected to the carrier.
13. The system as claimed in claim 9 wherein:
the integrated circuit includes a flip chip; and further comprising:
an underfill between the flip chip and the interposer.