IP Library Granted Patent US 8,129,832
Granted Patent B2
US 8,129,832 · App. 11/927,646 · Granted Mar 6, 2012

Mountable integrated circuit package system with substrate having a conductor-free recess

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,129,832
App. No.
11/927,646
Granted
Mar 6, 2012
Kind
B2
Abstract

A mountable integrated circuit package system includes: providing a carrier; mounting a first integrated circuit device over the carrier; mounting a substrate over the first integrated circuit device with the substrate having a conductor-free recess; connecting a first electrical interconnect under the conductor-free recess electrically connecting the carrier and the first integrated circuit device; and forming a package encapsulation over the carrier, the first integrated circuit device, the first electrical interconnect, the conductor-free recess, and partially exposing the substrate.

Claims (38)

1. A mountable integrated circuit package system comprising:

providing a carrier;

mounting a first integrated circuit device over the carrier;

mounting a substrate over the first integrated circuit device with the substrate having a conductor-free recess extending to a lateral edge of the substrate;

connecting a first electrical interconnect under the conductor-free recess electrically connecting the carrier and the first integrated circuit device; and

forming a package encapsulation over the carrier, the first integrated circuit device, the first electrical interconnect, the conductor-free recess, and partially exposing the substrate.

2. The system as claimed in claim 1 wherein mounting the substrate having the conductor-free recess includes mounting the substrate with the conductor-free recess not to a lateral edge of the substrate.

3. The system as claimed in claim 1 further comprising forming a spacer between the substrate and the first integrated circuit device.

4. The system as claimed in claim 1 further comprising mounting a second integrated circuit device over the substrate.

5. A mountable integrated circuit package system comprising:

providing a carrier, the carrier having a first carrier side and a second carrier side opposing the first carrier side;

mounting a first integrated circuit device over the first carrier side, with a non-active side of the first integrated circuit device facing the first carrier side;

mounting a substrate over the first integrated circuit device, the substrate having a first substrate side and a second substrate side opposing the first substrate side, the second substrate side having a conductor-free recess extending to a lateral edge of the substrate

connecting a first electrical interconnect under the conductor-free recess for connecting the carrier and an active side of the first integrated circuit device; and

forming a package encapsulation over the first carrier side, the first integrated circuit device, the first electrical interconnect, the conductor-free recess, and partially exposing the first substrate side.

6. The system as claimed in claim 5 wherein forming the package encapsulation includes exposing a first external interconnect of the substrate.

7. The system as claimed in claim 5 further comprising attaching a second external interconnect to the second carrier side.

8. The system as claimed in claim 5 further comprising connecting a second electrical interconnect between the carrier and the substrate.

9. The system as claimed in claim 5 wherein forming the package encapsulation includes:

exposing a first external interconnect on the first substrate side; and

further comprising:

mounting a second integrated circuit device over the first external interconnect.

10. A mountable integrated circuit package system comprising:

a carrier;

a first integrated circuit device mounted over the carrier;

a substrate mounted over the first integrated circuit device with the substrate having a conductor-free recess extending to a lateral edge of the substrate

a first electrical interconnect under the conductor-free recess connecting the carrier and the first integrated circuit device; and

a package encapsulation formed over the carrier, the first integrated circuit device, the first electrical interconnect, the conductor-free recess, and partially exposing the substrate.

11. The system as claimed in claim 10 wherein the conductor-free recess extends not to a lateral edge of the substrate.

12. The system as claimed in claim 10 further including a spacer between the substrate and an active side of the first integrated circuit device.

13. The system as claimed in claim 10 further comprising a second integrated circuit device mounted over the substrate.

14. The system as claimed in claim 10 wherein the substrate further includes a first substrate side and a second substrate side opposing the first substrate side, with the conductor-free recess formed on the second substrate side facing an active side of the first integrated circuit device.

15. The system as claimed in claim 14 wherein the package encapsulation exposes a first external interconnect on the first substrate side.

16. The system as claimed in claim 14 further comprising a second external interconnect attached to a second carrier side of the carrier opposing a first carrier side of the carrier.

17. The system as claimed in claim 14 further comprising a second electrical interconnect between the carrier and the substrate.

18. The system as claimed in claim 14 wherein the package encapsulation includes:

a first external interconnect exposed on the first substrate side; and

a second integrated circuit device mounted over the first external interconnect.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0474 ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 8, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064842/0046 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38378 FRAME: 0280) Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0474 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0280 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2007
From: CARSON, FLYNN; YOON, IN SANG; LEE, SEONGMIN; BAE, JOHYUN
To: STATS CHIPPAC LTD.
Reel/Frame 020032/0332 →