IP Library Granted Patent US 8,124,451
Granted Patent B2
US 8,124,451 · App. 11/859,359 · Granted Feb 28, 2012

Integrated circuit packaging system with interposer

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Quick Facts
Patent No.
US 8,124,451
App. No.
11/859,359
Granted
Feb 28, 2012
Kind
B2
Abstract

An integrated circuit packaging system comprising: fabricating an interposer array having an access opening; fabricating a base package substrate sheet; attaching a first integrated circuit die over the base package substrate sheet; mounting the interposer array over the first integrated circuit die; and singulating a base package from the base package substrate sheet and the interposer array by cutting the access opening generally through the center.

Claims (24)

1. A method of manufacturing an integrated circuit packaging system comprising:

fabricating an interposer array having an access opening;

fabricating a base package substrate sheet having system interconnects on lower surface contacts;

attaching a first integrated circuit die over the base package substrate sheet;

attaching a second integrated circuit die over the first integrated circuit die;

mounting the interposer array over the first integrated circuit die; and the second integrated circuit die;

molding an encapsulant, for covering the first integrated circuit die, the second integrated circuit die, and the base package substrate sheet, through the access opening including a top portion of the interposer array exposed from the encapsulant; and

singulating a base package from the base package substrate sheet and the interposer array by singulating the interposer array, substantially through the center of the access opening, and the base package substrate sheet, between the system interconnects, with a singulation device including exposing an interposer having recessed edges and corners exposed on a singulation edge.

2. The method as claimed in claim 1 further comprising coupling electrical interconnects through the access opening between the interposer array and the base package substrate sheet.

3. The method as claimed in claim 1 wherein molding the encapsulant through the access opening includes forming a base package array.

4. The method as claimed in claim 1 wherein mounting the second integrated circuit die over the first integrated circuit die includes coupling an electrical interconnect between the second integrated circuit die and the base package substrate sheet.

5. The method as claimed in claim 1 further comprising forming a contact array on the interposer array including interposer bonding contacts, interposer pin pads, interposer contacts, or a combination thereof.

6. A method of manufacturing an integrated circuit packaging system comprising:

fabricating an interposer array having an access opening including forming an interposer bonding contact adjacent to the access opening;

fabricating a base package substrate sheet having system interconnects on lower surface contacts including forming an upper surface contact on the base package substrate sheet;

attaching a first integrated circuit die over the base package substrate sheet including applying an adhesive between the base package substrate sheet and the first integrated circuit die;

attaching a second integrated circuit die over the integrated circuit die including applying an adhesive between the second integrated circuit die and the first integrated circuit die;

mounting the interposer array over the first integrated circuit die and the second integrated circuit die including applying the adhesive between the interposer array and the second integrated circuit die;

molding an encapsulant, for covering the first integrated circuit die, the second integrated circuit die, and the base package substrate sheet, through the access opening including a top portion of the interposer array exposed from the encapsulant; and

singulating a base package from the base package substrate sheet and the interposer array by singulating the interposer array, substantially through the center of the access opening, and the base package substrate sheet, between the system interconnects, with a singulation device including exposing an interposer having recessed edges and corners exposed on a singulation edge.

7. The method as claimed in claim 6 further comprising coupling electrical interconnects through the access opening between the interposer array and the base package substrate sheet including coupling the second integrated circuit die to the first integrated circuit die, the base package substrate sheet, the interposer array, or a combination thereof.

8. The method as claimed in claim 6 wherein molding the encapsulant through the access opening includes forming a base package array including encasing an electrical interconnect and a portion of the interposer array.

9. The method as claimed in claim 6 wherein mounting the second integrated circuit die over the first integrated circuit die in which mounting the second integrated circuit die includes coupling an electrical interconnect between the second integrated circuit die and the base package substrate sheet for forming an electrical connection between the first integrated circuit die, the second integrated circuit die, the base package substrate sheet, the interposer array, or a combination thereof.

10. The method as claimed in claim 6 further comprising forming a contact array on the interposer array including interposer bonding contacts, interposer pin pads, interposer contacts, or a combination thereof including molding the encapsulant over the interposer bonding contacts and not on the interposer pin pads or the interposer contacts.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0474 ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 8, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064842/0046 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38378 FRAME: 0280) Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0474 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0280 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2007
From: SONG, SUNGMIN; LEE, SEONGMIN; KO, WONJUN
To: STATS CHIPPAC LTD.
Reel/Frame 019861/0661 →