IP Library Granted Patent US 8,129,827
Granted Patent B2
US 8,129,827 · App. 11/855,114 · Granted Mar 6, 2012

Integrated circuit package system with package encapsulation having recess

Assignee: Stats Chippac Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,129,827
App. No.
11/855,114
Granted
Mar 6, 2012
Kind
B2
Abstract

An integrated circuit package system includes: forming an external interconnect; connecting an integrated circuit die and the external interconnect; forming a package encapsulation, having a recess, covering the integrated circuit die with a portion of the external interconnect exposed by the recess; and connecting an integrated circuit device and the external interconnect in the recess.

Claims (47)

1. A method of manufacturing an integrated circuit package system comprising:

forming an external interconnect;

connecting an integrated circuit die and the external interconnect;

forming a package encapsulation covering the integrated circuit die with an inner portion of the external interconnect in a recess of the package encapsulation including not covering the interior portion of the external interconnect by the package encapsulation; and

connecting an integrated circuit device and the external interconnect, on the interior portion, in the recess including not covering or contacting the integrated circuit device by the package encapsulation, the external interconnect attached between the integrated circuit device and the integrated circuit die.

2. The method as claimed in claim 1 wherein:

forming the external interconnect includes:

forming a die-attach paddle; and

further comprising:

mounting the integrated circuit die to the die-attach paddle.

3. The method as claimed in claim 1 further comprising:

forming a mounting structure over the external interconnect with the mounting structure having a material not included in the external interconnect; and

mounting the integrated circuit die over the mounting structure.

4. The method as claimed in claim 1 further comprising:

forming an adhesive layer over the external interconnect; and

mounting the integrated circuit die over the adhesive layer.

5. The method as claimed in claim 1 further comprising:

forming an inner tip exposed in the recess;

connecting the integrated circuit die and the inner tip; and

wherein connecting the integrated circuit device and the external interconnect in the recess includes:

connecting the integrated circuit device and the inner tip in the recess.

6. A method of manufacturing an integrated circuit package system comprising:

forming an external interconnect;

connecting an integrated circuit die to the external interconnect;

forming a package encapsulation for covering the integrated circuit die with the external interconnect partially exposed by a recess of the package encapsulation including not covering an interior portion on the external interconnect, at an opposing side with the integrated circuit die, by the package encapsulation; and

connecting an integrated circuit device and the external interconnect, on the interior portion, in the recess including not covering or contacting the integrated circuit device by the package encapsulation, the external interconnect attached between the integrated circuit device and the integrated circuit die.

7. The method as claimed in claim 6 wherein connecting the integrated circuit device and the external interconnect in the recess includes mounting the integrated circuit device over the integrated circuit die.

8. The method as claimed in claim 6 further comprising forming an inner encapsulation for covering the integrated circuit device in the recess.

9. The method as claimed in claim 6 wherein forming the package encapsulation includes forming a channel in the package encapsulation adjacent to the external interconnect in the recess.

10. The method as claimed in claim 6 wherein connecting the integrated circuit device includes mounting a packaged integrated circuit.

11. An integrated circuit package system comprising:

an external interconnect;

an integrated circuit die connected with the external interconnect;

a package encapsulation for covering the integrated circuit die with an interior portion of the external interconnect in a recess of the package encapsulation in which the interior portion of the external interconnect is not covered by the package encapsulation; and

an integrated circuit device mounted on the interior portion and connected with the external interconnect in the recess includes the integrated circuit device is not covered by and does not contact the package encapsulation, the external interconnect attached between the integrated circuit device and the integrated circuit die.

12. The system as claimed in claim 11 further comprising a die-attach paddle with the integrated circuit die mounted to the die-attach paddle.

13. The system as claimed in claim 11 further comprising a mounting structure over the external interconnect with the mounting structure having a material not included in the external interconnect and the integrated circuit die over the mounting structure.

14. The system as claimed in claim 11 further comprising an adhesive layer over the external interconnect with the integrated circuit die over the adhesive layer.

15. The system as claimed in claim 11 further comprising:

an inner tip exposed in the recess with the integrated circuit die connected with the inner tip; and

wherein the integrated circuit device connected with the external interconnect in the recess includes:

the integrated circuit device connected with the inner tip in the recess.

16. The system as claimed in claim 11 wherein the package encapsulation includes the recess with the mounting surface, on the external interconnect at an opposing side from the integrated circuit die, not covered by the package encapsulation.

17. The system as claimed in claim 16 wherein the integrated circuit device is over the integrated circuit die.

18. The system as claimed in claim 16 further comprising an inner encapsulation for covering the integrated circuit device in the recess.

19. The system as claimed in claim 16 wherein the package encapsulation includes a channel adjacent to the external interconnect in the recess.

20. The system as claimed in claim 16 wherein the integrated circuit device is a packaged integrated circuit.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0474 ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 8, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064842/0046 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38378 FRAME: 0280) Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0474 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0280 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2007
From: CAMACHO, ZIGMUND RAMIREZ; PUNZALAN, JEFFREY D.; PISIGAN, JAIRUS LEGASPI; ADVINCULA, ABELARDO JR HADAP
To: STATS CHIPPAC LTD.
Reel/Frame 019823/0985 →
Continuity (1)
Related Publication 20090072412A1 · Mar 19, 2009