IP Library Granted Patent US 8,134,196
Granted Patent B2
US 8,134,196 · App. 11/469,576 · Granted Mar 13, 2012

Integrated circuit system with metal-insulator-metal circuit element

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Quick Facts
Patent No.
US 8,134,196
App. No.
11/469,576
Granted
Mar 13, 2012
Kind
B2
Abstract

An integrated circuit system is provided including forming a substrate, forming a first contact having multiple conductive layers over the substrate and a layer of the multiple conductive layers on other layers of the multiple conductive layers, forming a dielectric layer on the first contact, and forming a second contact on the dielectric layer and over the first contact.

Claims (55)

1. A method of manufacturing an integrated circuit comprising:

forming a substrate;

forming a first contact having multiple conductive layers over the substrate and a layer of the multiple conductive layers directly contacts and covers other layers of the multiple conductive layers, wherein the other layers of the multiple conductive layers are entirely planar and the other layers having a first conductive layer, a second conductive layer, and a third conductive layer, with the first conductive layer 15 to 5 times thicker than the second conductive layer and the third conductive layer 5 to 15 times thicker than the second conductive layer;

forming a dielectric layer on the first contact; and

forming a second contact on the dielectric layer and over the first contact.

2. The method as claimed in claim 1 wherein forming the first contact having the multiple conductive layers includes forming layers with not all of the same material.

3. The method as claimed in claim 1 wherein forming the first contact having the multiple conductive layers includes:

forming the first conductive layer over the substrate;

forming the second conductive layer on the first conductive layer; and

forming the third conductive layer on the second conductive layer.

4. The method as claimed in claim 1 wherein forming the first contact having the multiple conductive layers includes:

forming the first conductive layer over the substrate;

forming the second conductive layer on the first conductive layer;

forming the third conductive layer on the second conductive layer; and

forming a fourth conductive layer on the third conductive layer.

5. The method as claimed in claim 1 further comprising forming a metal-insulator-metal capacitor with the first contact connected as a first electrode and the second contact connected as a second electrode.

6. A method of manufacturing an integrated circuit comprising:

forming a substrate;

forming a first conductive layer that is entirely planar over the substrate;

forming a second conductive layer that is entirely planar on the first conductive layer with the second conductive layer 15 to 5 times thinner than the first conductive layer;

forming a third conductive layer that is entirely planar on the second conductive layer with the third conductive layer 5 to 15 times thicker than the second conductive layer;

forming a fourth conductive layer directly contacting and covering the third conductive layer, the second conductive layer, and the first conductive layer;

forming a dielectric layer on the fourth conductive layer; and

forming an electrode on the dielectric layer and over the third conductive layer.

7. The method as claimed in claim 6 wherein:

forming the first conductive layer includes forming the first conductive layer comprised of copper and aluminum; and

forming the third conductive layer includes forming the third conductive layer comprised of copper and aluminum.

8. The method as claimed in claim 6 wherein forming the second conductive layer includes forming a layer comprised of nickel and vanadium.

9. The method as claimed in claim 6 wherein forming the fourth conductive layer includes forming a layer comprised of tantalum and silicon.

10. The method as claimed in claim 6 wherein forming the electrode includes forming the electrode comprised of copper and aluminum.

11. An integrated circuit system comprising:

a substrate;

a first contact having multiple conductive layers over the substrate and a layer of the multiple conductive layers directly contacts and covers other layers of the multiple conductive layers, wherein the other layers of the multiple conductive layers are entirely planar and the other layers having a first conductive layer, a second conductive layer, and a third conductive layer, with the first conductive layer 15 to 5 times thicker than the second conductive layer and the third conductive layer 5 to 15 times thicker than the second conductive layer;

a dielectric layer on the first contact; and

a second contact on the dielectric layer and over the first contact.

12. The system as claimed in claim 11 wherein the first contact having the multiple conductive layers has layers with not all of the same material.

13. The system as claimed in claim 11 wherein the first contact having the multiple conductive layers has:

the first conductive layer over the substrate;

the second conductive layer on the first conductive layer; and

the third conductive layer on the second conductive layer.

14. The system as claimed in claim 11 wherein the first contact having the multiple conductive layers has:

the first conductive layer over the substrate;

the second conductive layer on the first conductive layer;

the third conductive layer on the second conductive layer; and

a fourth conductive layer on the third conductive layer.

15. The system as claimed in claim 11 further comprising a metal-insulator-metal capacitor with the first contact connected as a first electrode and the second contact connected as a second electrode.

16. The system as claimed in claim 11 wherein:

the substrate is a silicon substrate;

the first contact having a fourth conductive layer with the fourth conductive layer directly contacting and covering the first conductive layer, the second conductive layer, and the third conductive layer;

the dielectric layer is comprised of silicon and nitrogen on the first contact; and

the second contact is an electrode on the dielectric layer and over the third conductive layer.

17. The system as claimed in claim 16 wherein the first conductive layer and the third conductive layer are comprised of copper and aluminum.

18. The system as claimed in claim 16 wherein the second conductive layer is comprised of nickel and vanadium.

19. The system as claimed in claim 16 wherein the fourth conductive layer is comprised of tantalum and silicon.

20. The system as claimed in claim 16 wherein the electrode is comprised of copper and aluminum.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0474 ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 8, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064842/0046 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38378 FRAME: 0280) Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0474 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0280 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2012
From: LIN, YAOJIAN; CAO, HAIJING; LOOI, WAN LAY; LIM, ENG SENG
To: STATS CHIPPAC LTD.
Reel/Frame 027687/0461 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 24, 2006
From: LIN, YAOJIAN; CAO, HAIJING; LOOI, WAN LAY; LIM, ENG SENG
To: STATS CHIPPAC LTD.
Reel/Frame 018549/0822 →