IP Library Granted Patent US 8,129,845
Granted Patent B2
US 8,129,845 · App. 12/207,324 · Granted Mar 6, 2012

Semiconductor device and method of forming interconnect structure in non-active area of wafer

Assignee: STATS ChipPAC, Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,129,845
App. No.
12/207,324
Granted
Mar 6, 2012
Kind
B2
Abstract

A semiconductor wafer includes a plurality of semiconductor die. Contact pads are formed on an active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. Solder bumps are formed on the contact pads in both the active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. The I/O terminal count of the semiconductor die is increased by forming solder bumps in the non-active area of the wafer. An encapsulant is formed over the solder bumps. The encapsulant provides structural support for the solder bumps formed in the non-active area of the semiconductor wafer. The semiconductor wafer undergoes grinding after forming the encapsulant to expose the solder bumps. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a package substrate with solder paste or socket.

Claims (56)

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor die;

forming contact pads in an active area of the semiconductor die and in a non-active area of the semiconductor wafer between the semiconductor die;

forming conductive bumps on the contact pads in the active area of the semiconductor die and in the non-active area of the semiconductor wafer between the semiconductor die;

forming an encapsulant over the conductive bumps;

singulating the semiconductor wafer to separate the semiconductor die; and

mounting the semiconductor die to a package substrate.

2. The method of claim 1 , wherein the encapsulant provides structural support for the conductive bumps formed in the non-active area of the semiconductor wafer between the semiconductor die.

3. The method of claim 1 , further including mounting the semiconductor die to the package substrate with solder paste.

4. The method of claim 1 , further including:

providing a socket base on the package substrate;

mounting the semiconductor die to the socket base; and

electrically connecting the conductive bumps to electrodes on the socket base.

5. The method of claim 1 , further including grinding the semiconductor wafer after forming the encapsulant to expose the conductive bumps.

6. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor die;

forming contact pads in a non-active area of the semiconductor wafer between the semiconductor die;

forming an interconnect structure on the contact pads in the non-active area of the semiconductor wafer between the semiconductor die; and

forming an encapsulant over the interconnect structure.

7. The method of claim 6 , wherein the interconnect structure includes conductive bumps, conductive posts, or wire bond sites.

8. The method of claim 6 , further including forming the interconnect structure in the active area of the semiconductor die.

9. The method of claim 6 , further including:

singulating the semiconductor wafer to separate the semiconductor die; and

mounting the semiconductor die to a package substrate.

10. The method of claim 6 , wherein the encapsulant provides structural support for the interconnect structure formed in the non-active area of the semiconductor wafer between the semiconductor die.

11. The method of claim 6 , further including mounting the semiconductor die to the package substrate with solder paste.

12. The method of claim 6 , further including:

providing a socket base on the package substrate;

mounting the semiconductor die to the socket base; and

electrically connecting the interconnect structure to electrodes on the socket base.

13. The method of claim 6 , further including grinding the semiconductor wafer after forming the encapsulant to expose the interconnect structure.

14. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor die;

forming an interconnect structure in a non-active area of the semiconductor wafer between the semiconductor die; and

forming an encapsulant over the interconnect structure.

15. The method of claim 14 , further including:

forming contact pads in the non-active area of the semiconductor wafer between the semiconductor die; and

forming the interconnect structure on the contact pads in the non-active area of the semiconductor wafer between the semiconductor die.

16. The method of claim 14 , wherein the interconnect structure includes conductive bumps, conductive posts, or wire bond sites.

17. The method of claim 14 , further including:

singulating the semiconductor wafer to separate the semiconductor die; and

mounting the semiconductor die to a package substrate.

18. The method of claim 14 , wherein the encapsulant provides structural support for the interconnect structure formed in the non-active area of the semiconductor wafer between the semiconductor die.

19. The method of claim 14 , further including mounting the semiconductor die to the package substrate with solder paste.

20. The method of claim 14 , further including:

providing a socket base on the package substrate;

mounting the semiconductor die to the socket base; and

electrically connecting the interconnect structure to electrodes on the socket base.

21. The method of claim 14 , further including grinding the semiconductor wafer after forming the encapsulant to expose the interconnect structure.

22. A semiconductor device, comprising:

a semiconductor wafer including a plurality of semiconductor die;

an interconnect structure formed in a non-active area of the semiconductor wafer between the semiconductor die; and

an encapsulant formed over the interconnect structure.

23. The semiconductor device of claim 22 , further including a plurality of contact pads formed on the non-active area of the semiconductor wafer between the semiconductor die, the interconnect structure being formed on the contact pads in the non-active area of the semiconductor wafer between the semiconductor die.

24. The semiconductor device of claim 22 , wherein the interconnect structure includes conductive bumps, conductive posts, or wire bond sites.

25. The semiconductor device of claim 22 , wherein the encapsulant provides structural support for the interconnect structure formed in the non-active area of the semiconductor wafer between the semiconductor die.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0474 ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 8, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064842/0046 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38378 FRAME: 0280) Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0474 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0280 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2008
From: JANG, TAEHOAN; KU, JAEHUN; BAO, XUSHENG
To: STATS CHIPPAC, LTD.
Reel/Frame 021505/0181 →
Continuity (2)
Provisional Application 60975124 · Sep 25, 2007
Related Publication 20090079069A1 · Mar 26, 2009