Patent Assignment
Reel/Frame 052864/0057
Release of Security Interest
Recorded: 2020-06-08
Received: 2020-06-08
Pages: 27
Assignor
CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Executed: 2019-05-03
Assignees
STATS CHIPPAC, INC.
46429 LANDING PARKWAY, FREMONT, CA, 94538, UNITED STATES
STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, 768442, SINGAPORE
Covered Properties
(100)
Multi-Level Optical Cassette
Application:
16/540,681 →
Integrated Circuit Packaging System with Interposer
Application:
13/397,562 →
Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure
Application:
13/241,153 →
Apparatus for Thermally Enhanced Semiconductor Package
Application:
13/212,986 →
Method for Manufacturing Integrated Circuit Package System with Under Paddle Leadfingers
Application:
13/172,560 →
Integrated Circuit Package in Package System
Application:
13/166,417 →
Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors
Application:
13/155,312 →
Integrated Circuit Packaging System with Lead Frame and Method of Manufacture Thereof
Application:
13/117,500 →
Integrated Circuit Packaging System with Mountable Inward and Outward Interconnects and Method of Manufacture Thereof
Application:
13/090,192 →
Bump-On-Lead Flip Chip Interconnection
Application:
13/088,647 →
Integrated Circuit Packaging System with Conductive Pillars and Method of Manufacture Thereof
Application:
13/080,070 →
Semiconductor Package System with Fine Pitch Lead Fingers and Method of Manufacturing Thereof
Application:
13/053,141 →
Integrated Circuit Package System Employing Device Stacking
Application:
13/039,311 →
Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive via and Exposed Bump
Application:
13/035,617 →
Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation
Application:
13/029,936 →
Integrated Circuit Package System for Electromagnetic Isolation and Method for Manufacturing Thereof
Application:
13/028,501 →
Method for Manufacturing Semiconductor Package System with Die Support Pad
Application:
13/023,329 →
Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers
Application:
13/019,562 →
Structure for Bumped Wafer Test
Application:
13/019,643 →
Semiconductor Device and Method of Forming Holes in Substrate to Interconnect Top Shield and Ground Shield
Application:
13/019,541 →
Method for Manufacturing Package System Incorporating Flip-Chip Assembly
Application:
12/976,753 →
Wire Bonding Structure and Method That Eliminates Special Wire Bondable Finish and Reduces Bonding Pitch on Substrates
Application:
12/973,410 →
Package-On-Package System with via Z-Interconnections and Method for Manufacturing Thereof
Application:
12/970,755 →
Integrated Circuit Packaging System with Bump Conductors and Method of Manufacture Thereof
Application:
12/968,257 →
Integrated Circuit Packaging System with Pad Connection and Method of Manufacture Thereof
Application:
12/961,490 →
Semiconductor Package with Semiconductor Core Structure and Method of Forming the Same
Application:
12/950,591 →
Encapsulant Interposer System with Integrated Passive Devices and Manufacturing Method Therefor
Application:
12/942,084 →
Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier
Application:
12/912,467 →
Semiconductor Device and Method of Providing a Thermal Dissipation Path Through Rdl and Conductive Via
Application:
12/911,042 →
Integrated Circuit Packaging System with Encapsulant Containment and Method of Manufacture Thereof
Application:
12/882,856 →
Semiconductor Device and Method of Forming Mold Underfill Using Dispensing Needle Having Same Width as Semiconductor Die
Application:
12/882,083 →
Integrated Circuit Packaging System with Pad Connection and Method of Manufacture Thereof
Application:
12/859,049 →
Semiconductor Device and Method of Forming Conductive Pillars in Recessed Region of Peripheral Area Around the Device for Electrical Interconnection to Other Devices
Application:
12/832,821 →
Quad Flat Pack in Quad Flat Pack Integrated Circuit Package System and Method for Manufacturing Thereof
Application:
12/827,864 →
Integrated Circuit Package System with Leaded Package and Method for Manufacturing Thereof
Application:
12/822,954 →
Integrated Circuit Packaging System with Encapsulation and Underfill and Method of Manufacture Thereof
Application:
12/818,462 →
Integrated Circuit Package System with Multiple Device Units and Method for Manufacturing Thereof
Application:
12/797,922 →
Integrated Circuit Packaging System with Multipart Conductive Pillars and Method of Manufacture Thereof
Application:
12/796,668 →
Semiconductor Device and Method of Forming Thermally Conductive Layer Between Semiconductor Die and Build-Up Interconnect Structure
Application:
12/794,612 →
Integrated Circuit Package System Including Honeycomb Molding
Application:
12/789,456 →
Integrated Circuit Packaging System with Package-on-Package and Method of Manufacture Thereof
Application:
12/772,142 →
Integrated Circuit Packaging System with Leads and Method of Manufacture Thereof
Application:
12/732,465 →
Fusible I/O Interconnection Systems and Methods for Flip-Chip Packaging Involving Substrate-Mounted Stud Bumps
Application:
12/731,354 →
Integrated Circuit Package System with Package Stacking and Method of Manufacture Thereof
Application:
12/727,229 →
Semiconductor Device and Method of Forming Ipd in Fan-Out Level Chip Scale Package
Application:
12/713,018 →
Solder Joint Flip Chip Interconnection Having Relief Structure
Application:
12/643,180 →
Integrated Circuit Packaging System with Package Stacking and Method of Manufacture Thereof
Application:
12/641,319 →
Semiconductor Device and Method of Forming Pip with Inner Known Good Die Interconnected with Conductive Bumps
Application:
12/635,631 →
Integrated Circuit Package System with Removable Backing Element Having Plated Terminal Leads and Method of Manufacture Thereof
Application:
12/635,695 →
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
Application:
12/633,531 →
Semiconductor Device and Method of Forming Column Interconnect Structure to Reduce Wafer Stress
Application:
12/610,763 →
Integrated Circuit Package System with Leadframe Substrate
Application:
12/573,110 →
Integrated Circuit Packaging System with Encapsulated via and Method of Manufacture Thereof
Application:
12/563,514 →
Semiconductor Device and Method of Forming Integrated Passive Device
Application:
12/557,811 →
Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars
Application:
12/545,357 →
Semiconductor Device and Method of Mounting Die with Tsv in Cavity of Substrate for Electrical Interconnect of Fi-Pop
Application:
12/533,943 →
Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps
Application:
12/492,360 →
Integrated Circuit Packaging System with a Leadframe Having Radial-Segments and Method of Manufacture Thereof
Application:
12/488,043 →
Integrated Circuit Packaging System with Stacked Integrated Circuit and Method of Manufacture Thereof
Application:
12/488,383 →
Integrated Circuit Packaging System with Warpage Control System and Method of Manufacture Thereof
Application:
12/412,303 →
Flip Chip Interconnect Solder Mask
Application:
12/362,627 →
Semiconductor Device and Method of Forming a Conductive via-in-via Structure
Application:
12/332,318 →
Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for Ipd and Baseband Circuit Separated by High-Resistivity Molding Compound
Application:
12/329,789 →
Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area Around the Device for Electrical Interconnection to Other Devices
Application:
12/329,800 →
Memory Device System with Stacked Packages
Application:
12/207,493 →
Semiconductor Device and Method of Forming a Fan-Out Structure with Integrated Passive Device and Discrete Component
Application:
12/207,332 →
Exposed Interconnect for a Package on Package System
Application:
12/188,995 →
Integrated Circuit Package System with Chip on Lead
Application:
12/172,095 →
Integrated Circuit Package System with Internal Stacking Module
Application:
12/137,529 →
Integrated Circuit Package System for Stackable Devices
Application:
12/136,037 →
Integrated Circuit Package System with Leadfinger
Application:
12/134,179 →
Stackable Integrated Circuit Package System with Multiple Interconnect Interface
Application:
12/113,888 →
Integrated Circuit Package System with Step Mold Recess
Application:
12/053,751 →
Package in Package System Incorporating an Internal Stiffener Component
Application:
12/051,305 →
Integrated Circuit Package System with Heat Sink Spacer Structures
Application:
12/050,797 →
Integrated Circuit Package System with Integration Port
Application:
12/046,430 →
Integrated Circuit Package System with Penetrable Film Adhesive
Application:
12/035,493 →
System for Peeling Semiconductor Chips from Tape
Application:
12/018,065 →
Mountable Integrated Circuit Package System with Intra-Stack Encapsulation
Application:
11/965,653 →
Integrated Circuit Package System for Shielding Electromagnetic Interference
Application:
11/956,132 →
Integrated Circuit Package System with Offset Stacked Die and Method of Manufacture Thereof
Application:
11/950,216 →
Wafer Level Die Integration and Method
Application:
11/949,133 →
Integrated Circuit Package-on-Package System with Anti-Mold Flash Feature
Application:
11/947,303 →
Integrated Circuit Package System with Package Integration
Application:
11/938,371 →
Mountable Integrated Circuit Package System with Mounting Interconnects
Application:
11/934,069 →
Integrated Circuit Package System with Leads Separated from a Die Paddle
Application:
11/854,989 →
Nested Integrated Circuit Package on Package System
Application:
11/849,263 →
Semiconductor Package System with Patterned Mask Over Thermal Relief
Application:
11/773,951 →
Integrated Circuit Package in Package System with Adhesiveless Package Attach
Application:
11/769,691 →
Electronic System with Expansion Feature
Application:
11/750,715 →
Integrated Circuit Package System with Encapsulating Features
Application:
11/694,921 →
Integrated Circuit Package System with Lead Support
Application:
11/689,229 →
Integrated Circuit Package with Molded Cavity
Application:
11/670,714 →
Integrated Circuit Package System with Flashless Leads
Application:
11/670,899 →
Bridge Stack Integrated Circuit Package-on-Package System
Application:
11/616,878 →
Integrated Circuit Package System Employing Mold Flash Prevention Technology
Application:
11/615,919 →
Integrated Circuit Package System with Waferscale Spacer
Application:
11/465,706 →
Integrated Circuit Package System with Filled Wafer Recess
Application:
11/462,509 →
Hyper Thermally Enhanced Semiconductor Package System Comprising Heat Slugs on Opposite Surfaces of a Semiconductor Chip
Application:
11/164,209 →
Integrated Circuit Package System Using Etched Leadframe
Application:
11/163,305 →