Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structure

1. A semiconductor device, comprising:

a first interconnect structure;

a first semiconductor die having an active surface oriented towards and mounted to a first surface of the first interconnect structure;

a first encapsulant deposited over the first interconnect structure and first semiconductor die;

a second semiconductor die having an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface;

a plurality of first conductive pillars formed over the second surface of the first interconnect structure and around the second semiconductor die;

a second encapsulant deposited over the second semiconductor die and around the plurality of first conductive pillars; and

a second interconnect structure formed over the second encapsulant and electrically connected to the plurality of first conductive pillars and the first and second semiconductor die.

2. The semiconductor device of claim 1 , further including:

a plurality of second conductive pillars disposed over the first surface of the first interconnect structure, the first encapsulant being formed around the plurality of second conductive pillars; and

a third interconnect structure formed over the first encapsulant opposite the first interconnect structure and electrically connected to the plurality of second conductive pillars and the first interconnect structure.

3. The semiconductor device of claim 1 , wherein the second interconnect structure includes:

a conductive layer formed over the second encapsulant; and

bumps formed over the conductive layer and the plurality of first conductive pillars.

4. The semiconductor device of claim 1 , wherein the plurality of first conductive pillars protrudes from the second encapsulant.

5. The semiconductor device of claim 1 , wherein the plurality of first conductive pillars is recessed with respect to a portion of the second encapsulant over the second semiconductor die.

6. The semiconductor device of claim 1 , further including planarizing the first encapsulant to expose a back surface of the first semiconductor die or planarizing the second encapsulant to expose a back surface of the second semiconductor die.

7. A semiconductor device, comprising:

a first interconnect structure;

a first semiconductor die having an active surface oriented towards and mounted over a first surface of the first interconnect structure;

a first encapsulant deposited over the first interconnect structure and first semiconductor die;

a second semiconductor die having an active surface oriented towards and mounted over a second surface of the first interconnect structure opposite the first surface;

a plurality of first conductive pillars formed over the second surface of the first interconnect structure;

a second encapsulant deposited over the second semiconductor die and around the plurality of first conductive pillars; and

a second interconnect structure formed over the second encapsulant.

8. The semiconductor device of claim 7 , wherein the plurality of first conductive pillars is formed around the second semiconductor die.

9. The semiconductor device of claim 7 , further including:

a plurality of second conductive pillars disposed over the first surface of the first interconnect structure, the first encapsulant being formed around the plurality of second conductive pillars; and

a third interconnect structure formed over the first encapsulant opposite the first interconnect structure and electrically connected to the plurality of second conductive pillars and the first interconnect structure.

10. The semiconductor device of claim 7 , wherein the plurality of first conductive pillars protrudes from the second encapsulant.

11. The semiconductor device of claim 7 , wherein the plurality of first conductive pillars is recessed with respect to a portion of the second encapsulant over the second semiconductor die.

12. The semiconductor device of claim 7 , wherein the second interconnect structure includes:

a conductive layer formed over the second encapsulant; and

bumps formed over the conductive layer and the plurality of first conductive pillars.

13. The semiconductor device of claim 7 , further including a shielding layer formed over the first semiconductor die or second semiconductor die.

14. A semiconductor device, comprising:

a first interconnect structure;

a first semiconductor die mounted over a first surface of the first interconnect structure;

a first encapsulant deposited over the first interconnect structure and first semiconductor die;

a second semiconductor die mounted over a second surface of the first interconnect structure opposite the first surface;

a plurality of first conductive pillars formed over the second surface of the first interconnect structure; and

a second encapsulant deposited over the second semiconductor die and around the plurality of first conductive pillars.

15. The method of claim 14 , further including a second interconnect structure formed over the second encapsulant and electrically connected to the plurality of first conductive pillars and the first and second semiconductor die.

16. The method of claim 15 , further including:

a plurality of second conductive pillars disposed over the first surface of the first interconnect structure, the first encapsulant being formed around the plurality of second conductive pillars; and

a third interconnect structure formed over the first encapsulant opposite the first interconnect structure and electrically connected to the plurality of second conductive pillars and the first interconnect structure.

17. The semiconductor device of claim 14 , wherein the plurality of first conductive pillars is formed around the second semiconductor die.

18. The semiconductor device of claim 15 , wherein the second interconnect structure includes:

a conductive layer formed over the second encapsulant; and

bumps formed over the conductive layer and the plurality of first conductive pillars.

19. The semiconductor device of claim 14 , wherein the plurality of first conductive pillars protrude from the second encapsulant.

20. A semiconductor device, comprising:

a first interconnect structure;

a first semiconductor die mounted over a first surface of the first interconnect structure;

a second semiconductor die mounted over a second surface of the first interconnect structure opposite the first surface;

a plurality of first conductive pillars formed over the second surface of the first interconnect structure;

a first encapsulant deposited over the first interconnect structure and first semiconductor die;

a second encapsulant deposited over the second semiconductor die and around the plurality of first conductive pillars; and

a second interconnect structure formed over the second encapsulant and electrically connected to the plurality of first conductive pillars and the first and second semiconductor die.

21. The method of claim 20 , wherein the plurality of first conductive pillars protrudes from the second encapsulant.

22. A semiconductor device, comprising:

a first interconnect structure;

a first semiconductor die mounted over a first surface of the first interconnect structure;

a second semiconductor die mounted over a second surface of the first interconnect structure opposite the first surface;

a plurality of first conductive pillars formed over the second surface of the first interconnect structure; and

a shielding layer formed over the first semiconductor die or second semiconductor die.

23. The semiconductor device of claim 20 , further including planarizing the first encapsulant to expose a back surface of the first semiconductor die or planarizing the second encapsulant to expose a back surface of the second semiconductor die.