Patent Assignment
Reel/Frame 065236/0784
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0252. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.
Recorded: 2023-08-31
Received: 2023-10-16
Pages: 11
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Applications
(70)
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLARS IN RECESSED REGION OF PERIPHERAL AREA AROUND THE DEVICE FOR ELECTRICAL INTERCONNECTION TO OTHER DEVICES
App. No. 13/423,263
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED INTERCONNECT LAYER FOR STACKED SEMICONDUCTOR DIE
App. No. 13/350,299
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METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT
App. No. 13/300,088
→
SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURE
App. No. 13/241,153
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SOLDER BUMP WITH INNER CORE PILLAR IN SEMICONDUCTOR PACKAGE
App. No. 13/237,828
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A COMPONENT IN AN ENCAPSULANT CAVITY AND METHOD OF FABRICATION THEREOF
App. No. 13/235,755
→
PACKAGE-ON-PACKAGE SYSTEM WITH THROUGH VIAS AND METHOD OF MANUFACTURE THEREOF
App. No. 13/169,387
→
SEMICONDUCTOR DEVICE AND METHOD OF USING LEADFRAME BODIES TO FORM OPENINGS THROUGH ENCAPSULANT FOR VERTICAL INTERCONNECT OF SEMICONDUCTOR DIE
App. No. 13/153,286
→
INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
App. No. 13/095,680
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METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS
App. No. 13/081,227
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CONDUCTIVE STRUCTURE AND METHOD OF MANUFACTURE THEREOF
App. No. 13/070,219
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER SEMICONDUCTOR DIE MOUNTED TO TSV INTERPOSER
App. No. 13/043,179
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A WAFER LEVEL PACKAGE STRUCTURE USING CONDUCTIVE VIA AND EXPOSED BUMP
App. No. 13/035,617
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INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION AND METHOD FOR MANUFACTURING THEREOF
App. No. 13/028,501
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING HOLES IN SUBSTRATE TO INTERCONNECT TOP SHIELD AND GROUND SHIELD
App. No. 13/019,541
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WIRE BONDING STRUCTURE AND METHOD THAT ELIMINATES SPECIAL WIRE BONDABLE FINISH AND REDUCES BONDING PITCH ON SUBSTRATES
App. No. 12/973,410
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP CONDUCTORS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/968,257
→
ENCAPSULANT INTERPOSER SYSTEM WITH INTEGRATED PASSIVE DEVICES AND MANUFACTURING METHOD THEREFOR
App. No. 12/942,084
→
ULTRA THIN BUMPED WAFER WITH UNDER-FILM
App. No. 12/916,758
→
SEMICONDUCTOR DEVICE AND METHOD OF STACKING SEMICONDUCTOR DIE IN MOLD LASER PACKAGE INTERCONNECTED BY BUMPS AND CONDUCTIVE VIAS
App. No. 12/914,895
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERPOSER PACKAGE WITH THROUGH SILICON VIAS
App. No. 12/905,825
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/881,983
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH CAVITIES FORMED THROUGH ETCH-RESISTANT CONDUCTIVE LAYER FOR BUMP LOCKING
App. No. 12/878,661
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP WITH DISCRETE SEMICONDUCTOR COMPONENTS MOUNTED UNDER AND OVER SEMICONDUCTOR DIE
App. No. 12/868,334
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING FO-WLCSP HAVING CONDUCTIVE LAYERS AND CONDUCTIVE VIAS SEPARATED BY POLYMER LAYERS
App. No. 12/857,362
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED LEAD AND METHOD OF MANUFACTURE THEREOF
App. No. 12/854,306
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT IN FO-WLCSP USING LEADFRAME DISPOSED BETWEEN SEMICONDUCTOR DIE
App. No. 12/853,865
→
METHOD OF FORMING AN INDUCTOR ON A SEMICONDUCTOR WAFER
App. No. 12/826,365
→
SEMICONDUCTOR PACKAGING SYSTEM WITH MULTIPART CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/821,404
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND UNDERFILL AND METHOD OF MANUFACTURE THEREOF
App. No. 12/818,462
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RF FEM WITH LC FILTER AND IPD FILTER OVER SUBSTRATE
App. No. 12/816,225
→
FLIP CHIP INTERCONNECTION HAVING NARROW INTERCONNECTION SITES ON THE SUBSTRATE
App. No. 12/757,889
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING RF BALUN HAVING REDUCED CAPACITIVE COUPLING AND HIGH CMRR
App. No. 12/750,555
→
INTEGRATED CIRCUIT SYSTEM WITH STRESS REDISTRIBUTION LAYER AND METHOD OF MANUFACTURE THEREOF
App. No. 12/748,335
→
SEMICONDUCTOR PACKAGE SYSTEM WITH THERMAL DIE BONDING
App. No. 12/729,204
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/727,229
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING REPASSIVATION LAYER WITH REDUCED OPENING TO CONTACT PAD OF SEMICONDUCTOR DIE
App. No. 12/724,367
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELD AND METHOD OF MANUFACTURE THEREOF
App. No. 12/711,250
→
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING PASSIVE CIRCUIT ELEMENTS WITH THROUGH SILICON VIAS TO BACKSIDE INTERCONNECT STRUCTURES
App. No. 12/704,366
→
SEMICONDUCTOR DEVICE WITH SOLDER BUMP FORMED ON HIGH TOPOGRAPHY PLATED CU PADS
App. No. 12/700,114
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
App. No. 12/641,319
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BOND WIRE PADS AND METHOD OF MANUFACTURE THEREOF
App. No. 12/637,746
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELDED PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/636,703
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/636,696
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOOD DIE INTERCONNECTED WITH CONDUCTIVE BUMPS
App. No. 12/635,631
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PACKAGE SYSTEM WITH A SHIELDED INVERTED INTERNAL STACKING MODULE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/629,877
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
App. No. 12/618,417
→
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATED VIA AND METHOD OF MANUFACTURE THEREOF
App. No. 12/563,514
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH QUAD FLAT NO-LEAD PACKAGE AND METHOD OF MANUFACTURE THEREOF
App. No. 12/562,874
→
SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING DIE WITH TSV IN CAVITY OF SUBSTRATE FOR ELECTRICAL INTERCONNECT OF FI-POP
App. No. 12/533,943
→
FLIP CHIP INTERCONNECT SOLDER MASK
App. No. 12/362,627
→
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A CONDUCTIVE VIA-IN-VIA STRUCTURE
App. No. 12/332,318
→
MEMORY DEVICE SYSTEM WITH STACKED PACKAGES
App. No. 12/207,493
→
EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM
App. No. 12/188,995
→
FAN-IN INTERPOSER ON LEAD FRAME FOR AN INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
App. No. 12/185,061
→
SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING COMMON VOLTAGE BUS AND WIRE BONDABLE REDISTRIBUTION
App. No. 12/182,283
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CHIP ON LEAD
App. No. 12/172,095
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE
App. No. 12/137,529
→
PACKAGE IN PACKAGE SYSTEM INCORPORATING AN INTERNAL STIFFENER COMPONENT
App. No. 12/051,305
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SEMICONDUCTOR DEVICE WITH CROSS-TALK ISOLATION USING M-CAP AND METHOD THEREOF
App. No. 12/051,253
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRATION PORT
App. No. 12/046,430
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OVERHANG FILM
App. No. 12/037,343
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PENETRABLE FILM ADHESIVE
App. No. 12/035,493
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE INTEGRATION
App. No. 11/938,371
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADS SEPARATED FROM A DIE PADDLE
App. No. 11/854,989
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SEMICONDUCTOR PACKAGE SYSTEM WITH PATTERNED MASK OVER THERMAL RELIEF
App. No. 11/773,951
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD SUPPORT
App. No. 11/689,229
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STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM
App. No. 11/608,826
→
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FILLED WAFER RECESS
App. No. 11/462,509
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WAFER LEVEL LASER MARKING SYSTEM FOR ULTRA-THIN WAFERS USING SUPPORT TAPE
App. No. 11/163,156
→