Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
View Patent ↗A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer.
1. A method of making a semiconductor device, comprising:
providing a carrier;
mounting a plurality of first semiconductor die to the carrier;
forming an encapsulant over the carrier and around the first semiconductor die;
forming a plurality of conductive pillars through the encapsulant and adjacent to the first semiconductor die;
forming a first stepped interconnect structure over the encapsulant; and
mounting a plurality of second semiconductor die within a plurality of openings in the first stepped interconnect structure.
2. The method of claim 1 , further including:
removing the carrier; and
forming an interconnect structure on a surface of the encapsulant and first semiconductor die.
3. The method of claim 1 , further including:
forming a second stepped interconnect structure over the first stepped interconnect structure; and
mounting a third semiconductor die within an opening in the second stepped interconnect structure.
4. The method of claim 1 , further including mounting one of the second semiconductor die partially outside an opening in the first stepped interconnect structure.
5. The method of claim 1 , further including forming an opening in the first stepped interconnect structure that exposes one of the first semiconductor die.
6. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
forming an encapsulant around the first semiconductor die;
forming a plurality of conductive pillars through the encapsulant and disposed adjacent to the semiconductor die;
forming a stepped interconnect structure over the encapsulant; and
mounting a second semiconductor die within an opening in the stepped interconnect structure.
7. The method of claim 6 , further including mounting the second semiconductor die partially outside the opening in the stepped interconnect structure.
8. The method of claim 6 , further including mounting a third semiconductor die over the stepped interconnect structure and second semiconductor die.
9. The method of claim 6 , further including forming a conductive layer over a portion of the encapsulant, first semiconductor die, and conductive pillars.
10. The method of claim 6 , further including forming an opening in the first stepped interconnect structure that exposes the first semiconductor die.
11. The method of claim 6 , further including forming the stepped interconnect structure from a pre-formed substrate.
12. The method of claim 6 , further including forming a portion of the stepped interconnect structure over the first semiconductor die.
13. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
forming an encapsulant around the first semiconductor die;
forming a plurality of conductive pillars through the encapsulant and adjacent to the first semiconductor die;
forming a first stepped interconnect structure over a first surface of the encapsulant; and
forming a first opening in the first stepped interconnect structure, wherein the first opening is adapted for mounting a second semiconductor die within the first opening and over the first semiconductor die.
14. The method of claim 13 , further including:
forming a second stepped interconnect structure over the first stepped interconnect structure; and
forming a second opening in the second stepped interconnect structure, wherein the second opening is adapted for mounting a third semiconductor die within the second opening and over the first opening.
15. The method of claim 13 , further including forming an interconnect structure over a second surface of the encapsulant, the first semiconductor die, and the conductive pillars.
16. The method of claim 13 , further including forming the first opening so that the first opening is adapted for mounting the second semiconductor die partially outside the first opening.
17. The method of claim 13 , further including:
forming a conductive layer in an area exposed by the first opening; and
forming an insulating layer over a portion of the conductive layer.
18. The method of claim 13 , further including:
forming a conductive layer in an area exposed by the first opening, wherein
the first semiconductor die includes a through silicon via; and
the conductive layer is electrically connected to the through silicon via.
19. The method of claim 13 , further including forming the first stepped interconnect structure from a pre-formed substrate.