Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
View Patent ↗A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure.
1. A method of making a wafer level chip scale package (WLCSP), comprising:
providing a first polymer layer including a plurality of contact pads formed within the first polymer layer;
mounting the first polymer layer to a carrier;
mounting a semiconductor die to the first polymer layer;
forming a second polymer layer over the semiconductor die and first polymer layer;
forming a plurality of first conductive vias through the first and second polymer layers with the first conductive vias electrically connected to the contact pads within the first polymer layer;
forming a first conductive layer over the second polymer layer and electrically connected to the first conductive vias and semiconductor die;
forming a third polymer layer over the second polymer layer and first conductive layer;
forming a plurality of second conductive vias through the third polymer layer and electrically connected to the first conductive layer;
forming a second conductive layer over the third polymer layer and electrically connected to the second conductive vias; and
forming a first interconnect structure over the third polymer layer and second conductive layer.
2. The method of claim 1 , further including forming the first conductive vias around a perimeter of the semiconductor die.
3. The method of claim 1 , further including forming the contact pads around a perimeter of the semiconductor die.
4. The method of claim 1 , further including forming the contact pads under the semiconductor die.
5. The method of claim 1 , wherein forming the first interconnect structure includes:
forming an insulating layer over the third polymer layer and second conductive layer;
removing a portion of the insulating layer to expose the second conductive layer; and
forming a plurality of bumps over the exposed second conductive layer.
6. The method of claim 1 , further including:
providing a semiconductor package;
mounting the semiconductor package to the WLCSP; and
electrically connecting the semiconductor package to the WLCSP through the first interconnect structure.
7. The method of claim 1 , further including:
removing the carrier; and
forming a second interconnect structure over the first polymer layer and contact pads.
8. A method of making a wafer level chip scale package (WLCSP), comprising:
providing a first polymer layer including a plurality of contact pads formed within the first polymer layer;
mounting the first polymer layer over a carrier;
forming a plurality of first conductive vias through the first polymer layer and electrically connected to the contact pads;
forming a first conductive layer over the first polymer layer and electrically connected to the first conductive vias;
forming a second polymer layer over the first polymer layer;
mounting a semiconductor die to the second polymer layer;
forming a third polymer layer over the semiconductor die and second polymer layer;
forming a plurality of second conductive vias through the second and third polymer layers and electrically connected to the first conductive layer;
forming a second conductive layer over the third polymer layer and electrically connected to the second conductive vias and semiconductor die;
forming a fourth polymer layer over the third polymer layer and second conductive layer;
forming a plurality of third conductive vias through the fourth polymer layer and electrically connected to the second conductive layer;
forming a third conductive layer over the fourth polymer layer and electrically connected to the third conductive vias; and
forming a first interconnect structure over the fourth polymer layer and third conductive layer.
9. The method of claim 8 , further including:
forming the first conductive vias under the semiconductor die; and
forming the contact pads under the semiconductor die.
10. The method of claim 8 , further including forming the second conductive vias around a perimeter of the semiconductor die.
11. The method of claim 8 , wherein forming the first interconnect structure includes:
forming an insulating layer over the fourth polymer layer and third conductive layer;
removing a portion of the insulating layer to expose the third conductive layer; and
forming a plurality of bumps over the exposed third conductive layer.
12. The method of claim 8 , further including:
providing a semiconductor package;
mounting the semiconductor package to the WLCSP; and
electrically connecting the semiconductor package to the WLCSP through the first interconnect structure.
13. The method of claim 8 , further including:
removing the carrier; and
forming a second interconnect structure over the first polymer layer and contact pads.
14. A method of making a wafer level chip scale package (WLCSP), comprising:
providing a first polymer layer including a plurality of contact pads formed within the first polymer layer;
mounting a semiconductor die over the first polymer layer;
forming a second polymer layer around the semiconductor die;
forming a plurality of first conductive vias through the first and second polymer layers and electrically connected to the contact pads;
forming a first interconnect structure over a first surface of the second polymer layer and electrically connected to the first conductive vias; and
forming a second interconnect structure over a second surface of the second polymer layer opposite the first surface and electrically connected to the first conductive vias.
15. The method of claim 14 , wherein forming the first interconnect structure includes:
forming a plurality of second conductive vias through the first polymer layer and electrically connected to the contact pads;
forming a conductive layer over the first polymer layer and electrically connected to the second conductive vias; and
forming a third polymer layer over the first polymer layer.
16. The method of claim 15 , further including:
forming the second conductive vias under the semiconductor die; and
forming the contact pads under the semiconductor die.
17. The method of claim 14 , wherein forming the second interconnect structure includes:
forming a first conductive layer over the second polymer layer electrically connected to the first conductive vias and semiconductor die;
forming a third polymer layer over the first polymer layer and first conductive layer;
forming a plurality of second conductive vias through the third polymer layer and electrically connected to the first conductive layer; and
forming a second conductive layer over the third polymer layer and electrically connected to the second conductive vias.
18. The method of claim 14 , further including forming the first conductive vias around a perimeter of the semiconductor die.
19. The method of claim 14 , further including:
providing a semiconductor package;
mounting the semiconductor package to the WLCSP; and
electrically connecting the semiconductor package to the WLCSP through the first interconnect structure or second interconnect structure.
20. A wafer level chip scale package (WLCSP), comprising:
a first interconnect structure;
a plurality of contact pads exposed on a first surface of the first interconnect structure;
a semiconductor die mounted over a second surface of the interconnect structure opposite the first surface;
a first polymer layer formed around the semiconductor die;
a plurality of first conductive vias formed through the first polymer layer and electrically connected to the contact pads;
and
a second interconnect structure formed over a surface of the first polymer layer opposite the first interconnect structure and electrically connected between the first conductive vias and the semiconductor die.
21. The WLCSP of claim 20 , wherein the first interconnect structure includes:
a second polymer layer with the contact pads formed within the second polymer layer;
a plurality of second conductive vias formed through the second polymer layer and electrically connected to the contact pads;
a conductive layer formed over the second polymer layer and electrically connected to the second conductive vias; and
a third polymer layer formed over the second polymer layer.
22. The WLCSP of claim 20 , wherein the second interconnect structure includes:
a first conductive layer formed over the first polymer layer and electrically connected to the first conductive vias and semiconductor die;
a second polymer layer formed over the first polymer layer and first conductive layer;
a plurality of second conductive vias formed through the second polymer layer and electrically connected to the first conductive layer; and
a second conductive layer over the second polymer layer and electrically connected to the second conductive vias.
23. The WLCSP of claim 20 , further including a semiconductor package mounted to the WLCSP and electrically connected to the WLCSP through the first interconnect structure or second interconnect structure.
24. A method of making a wafer level chip scale package (WLCSP), comprising:
providing a first polymer layer including a contact pad formed within a first surface of the first polymer layer;
mounting a semiconductor die over a second surface of the first polymer layer opposite the first surface;
forming a second polymer layer over the first polymer layer and semiconductor die; and
forming a first conductive via through the first polymer layer and second polymer layer and electrically connected to the contact pad.
25. The WLCSP of claim 24 , further including forming an interconnect structure over the second polymer layer electrically connected to the first conductive via and the semiconductor die.
26. The WLCSP of claim 25 , wherein forming the interconnect structure further includes:
forming a conductive layer over the semiconductor die electrically connected to the first conductive via and the semiconductor die;
forming a third polymer layer over the conductive layer; and
forming a second conductive via through the third polymer layer electrically connected to the conductive layer.
27. The WLCSP of claim 24 , further including forming an interconnect structure over the first polymer layer electrically connected to the contact pad.
28. The WLCSP of claim 27 , wherein forming the interconnect structure further includes:
forming a third polymer layer over the first surface of the first polymer layer; and
forming a second conductive via through the third polymer layer electrically connected to the contact pad.
29. The WLCSP of claim 24 , further including forming a third polymer layer over the second surface of the first polymer layer prior to mounting the semiconductor die.
30. The WLCSP of claim 24 , further including mounting a semiconductor package over the WLCSP.