Integrated circuit packaging system with package-on-package and method of manufacture thereof

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a bottom substrate and a top substrate;

mounting a bottom integrated circuit over the bottom substrate;

forming an underfill material on the bottom substrate or the top substrate;

forming a patterned underfill by removing a portion of the underfill material;

mounting a top substrate over a side of the bottom integrated circuit opposite the bottom substrate; and

connecting a top interconnect between the bottom substrate and the top substrate and encapsulated by the patterned underfill outside a perimeter of the bottom integrated circuit.

2. The method as claimed in claim 1 wherein forming the underfill layer includes forming the underfill layer having thermal conduction.

3. The method as claimed in claim 1 wherein forming the underfill layer includes forming the underfill layer having a discontinuous structure adjacent a side of the top substrate.

4. The method as claimed in claim 1 wherein forming the underfill layer includes forming the underfill layer with a material providing fixed spacing between the bottom substrate and the top substrate.

5. The method as claimed in claim 1 further comprising applying a thermal interface layer directly on the bottom integrated circuit and thermally connected to the bottom integrated circuit and the top substrate.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a bottom substrate and a top substrate;

mounting a bottom integrated circuit over the bottom substrate;

forming an underfill material on the bottom substrate or the top substrate;

forming a patterned underfill by removing a portion of the underfill material;

mounting a top substrate over a side of the bottom integrated circuit opposite the bottom substrate, the top substrate having a periphery; and

connecting a top interconnect between the bottom substrate and the top substrate and encapsulated by the patterned underfill outside a perimeter of the bottom integrated circuit, the patterned underfill between the periphery and the bottom integrated circuit.

7. The method as claimed in claim 6 further comprising forming a bottom encapsulation over the bottom substrate and covering the bottom integrated circuit, the bottom encapsulation adjacent the underfill layer.

8. The method as claimed in claim 6 further comprising mounting a second bottom integrated circuit over the bottom integrated circuit.

9. The method as claimed in claim 6 wherein mounting the bottom integrated circuit includes mounting a flip chip over the bottom substrate.

10. The method as claimed in claim 6 wherein mounting the bottom integrated circuit includes mounting a wirebond device over the bottom substrate.

11. An integrated circuit packaging system comprising:

a bottom substrate;

a bottom integrated circuit over the bottom substrate;

a top substrate over a side of the bottom integrated circuit opposite the bottom substrate;

a top interconnect between the bottom substrate and the top substrate; and

an underfill layer, including a photoimageable material, between the bottom substrate and the top substrate, the underfill layer encapsulating the top interconnect, outside a perimeter of the bottom integrated circuit.

12. The system as claimed in claim 11 wherein the underfill layer has thermal conduction.

13. The system as claimed in claim 11 wherein the underfill layer includes a discontinuous structure adjacent a side of the top substrate.

14. The system as claimed in claim 11 wherein the underfill layer is a material providing fixed spacing between the bottom substrate and the top substrate.

15. The system as claimed in claim 11 further comprising a thermal interface layer directly on the bottom integrated circuit and thermally connected to the bottom integrated circuit and the top substrate.

16. The system as claimed in claim 11 wherein:

the top substrate includes a periphery; and

the underfill layer is between the periphery and the bottom integrated circuit.

17. The system as claimed in claim 16 further comprising a bottom encapsulation over the bottom substrate and covering the bottom integrated circuit, the bottom encapsulation adjacent the underfill layer.

18. The system as claimed in claim 16 further comprising a second bottom integrated circuit over the bottom integrated circuit.

19. The system as claimed in claim 16 wherein the bottom integrated circuit is a flip chip over the bottom substrate.

20. The system as claimed in claim 16 wherein the bottom integrated circuit is a wirebond device over the bottom substrate.