Integrated circuit packaging system with quad flat no-lead package and method of manufacture thereof
View Patent ↗A method of manufacture of an integrated circuit packaging system includes: providing a base array having terminals and an open region; attaching a coverlay layer directly on the base array; placing a component in the open region and directly on the coverlay layer; forming an encapsulation over the base array and the component; removing the coverlay layer to leave a plane of the terminals and a plane of the component partially exposed and substantially coplanar; and removing a portion of the base array between the terminals, the terminals electrically isolated.
1. A method of manufacture of an integrated circuit packaging system comprising:
providing a base array having terminals and an open region;
attaching a coverlay layer directly on the base array;
placing a component in the open region and directly on the coverlay layer;
forming an encapsulation over the base array and the component;
removing the coverlay layer to leave a plane of the terminals and a plane of the component partially exposed from and substantially coplanar with the encapsulation; and
removing a portion of the base array between the terminals to form an encapsulation step in the encapsulation adjacent the component and a recessed surface extending from the encapsulation step to an outer vertical side of the encapsulation, the terminals protruding from the recessed surface.
2. The method as claimed in claim 1 wherein providing the terminals includes forming the terminals in an array with multiple rows.
3. The method as claimed in claim 1 wherein placing the component includes placing a package in the open region and directly on the coverlay layer.
4. The method as claimed in claim 1 wherein placing the component includes placing a package in the open region and directly on the coverlay layer, the package having a paddle and a pad partially exposed from the encapsulation.
5. The method as claimed in claim 1 wherein placing the component includes placing a heatsink in the open region and directly on the coverlay layer.
6. A method of manufacture of an integrated circuit packaging system comprising:
providing a base array having terminals and an open region;
attaching a coverlay layer directly on the base array;
placing a component in the open region and directly on the coverlay layer;
mounting a stack component over the component;
forming an encapsulation over the base array, the component, and the stack component;
removing the coverlay layer to leave a plane of the terminals and a plane of the component partially exposed from and substantially coplanar with the encapsulation; and
removing a portion of the base array between the terminals to form an encapsulation step in the encapsulation adjacent the component and a recessed surface extending from the encapsulation step to an outer vertical side of the encapsulation, the terminals protruding from the recessed surface.
7. The method as claimed in claim 6 wherein providing the terminals includes forming the terminals in an array with multiple staggered rows.
8. The method as claimed in claim 6 wherein placing the component includes placing a multi-row quad flat no-lead package in the open region and directly on the coverlay layer.
9. The method as claimed in claim 6 wherein placing the component includes placing a package in the open region and directly on the coverlay layer, the package having a paddle and a pad with a planar surface substantially coplanar with that of the encapsulation.
10. The method as claimed in claim 6 wherein placing the component includes placing a heatsink in the open region and directly on the coverlay layer, the heatsink having an interlocking mechanism.
11. An integrated circuit packaging system comprising:
a base array having terminals and an open region;
a component in the open region, a plane of the terminals and a plane of the component substantially coplanar; and
an encapsulation, having an encapsulation step adjacent the component and a recessed surface extending from the encapsulation step to an outer vertical side of the encapsulation, over the base array and the component, the terminals protruding from the recessed surface.
12. The system as claimed in claim 11 wherein the terminals includes the terminals in an array with multiple rows.
13. The system as claimed in claim 11 wherein the component includes a package in the open region.
14. The system as claimed in claim 11 wherein the component includes a package in the open region, the package having a paddle and a pad partially exposed from the encapsulation.
15. The system as claimed in claim 11 wherein the component includes a heatsink in the open region.
16. The system as claimed in claim 11 further comprising a stack component over the component and covered by the encapsulation.
17. The system as claimed in claim 16 wherein the terminals includes the terminals in an array with multiple staggered rows.
18. The system as claimed in claim 16 wherein the component includes a multi-row quad flat no-lead package in the open region.
19. The system as claimed in claim 16 wherein the component includes a package in the open region, the package having a paddle and a pad along a surface of the component substantially coplanar with a planar surface of the encapsulation.
20. The system as claimed in claim 16 wherein the component includes a heatsink in the open region, the heatsink having an interlocking mechanism.