Semiconductor package system with thermal die bonding
A semiconductor package system includes providing a substrate having a plurality of thermal vias extending through the substrate. A solder mask is positioned over the plurality of thermal vias. A plurality of thermally conductive bumps is formed on at least some of the plurality of thermal vias using the solder mask. An integrated circuit die is attached to the plurality of thermally conductive bumps. An encapsulant encapsulates the integrated circuit die.
1. A semiconductor package system, comprising:
a substrate having a plurality of thermal vias extending through the substrate;
a plurality of thermally conductive bumps on at least some of the plurality of thermal vias;
an integrated circuit die having an inactive side attached to the plurality of thermally conductive bumps;
an encapsulant encapsulating the integrated circuit die;
a plurality of contacts on the upper and lower surfaces of the substrate; and
an interconnect array connecting the plurality of contacts on the upper and lower surfaces of the substrate.
2. The semiconductor package system as claimed in claim 1 , wherein:
the plurality of thermally conductive bumps comprises a thermally conductive material having a thermal conductivity greater than that of the substrate.
3. The semiconductor package system as claimed in claim 1 , wherein:
the plurality of thermally conductive bumps comprises at least one of a high thermal epoxy, a eutectic solder paste, a tin-silver solder paste, compounds thereof, alloys thereof, and combinations thereof.
4. The semiconductor package system as claimed in claim 1 , wherein:
the plurality of thermally conductive bumps on at least some of the plurality of thermal vias are in an array of at least one of a close packed array, an open array, and combinations thereof.
5. The semiconductor package system as claimed in claim 1 , wherein:
the plurality of thermal vias extending through the central portion of the substrate comprises a wettable surface on the plurality of thermal vias.
6. The semiconductor package system as claimed in claim 1 , wherein:
the plurality of thermally conductive bumps on at least some of the plurality of thermal vias are in an array of at least one of a close packed array, an open array, and combinations thereof.
7. The semiconductor package system as claimed in claim 1 , wherein:
the plurality of thermally conductive bumps comprises at least one of a high thermal epoxy, a eutectic solder paste, a tin-silver solder paste, compounds thereof, alloys thereof, and combinations thereof attaching the integrated circuit die to the plurality of thermal vias.