IP Library Granted Patent US 8,304,277
Granted Patent B2
US 8,304,277 · App. 12/878,661 · Granted Nov 6, 2012

Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking

Assignee: STATS ChipPAC, Ltd.
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Quick Facts
Patent No.
US 8,304,277
App. No.
12/878,661
Granted
Nov 6, 2012
Kind
B2
Abstract

A semiconductor device has a base substrate with first and second etch-resistant conductive layers formed over opposing surfaces of the base substrate. First cavities are etched in the base substrate through an opening in the first conductive layer. The first cavities have a width greater than a width of the opening in the first conductive layer. Second cavities are etched in the base substrate between portions of the first or second conductive layer. A semiconductor die is mounted over the base substrate with bumps disposed over the first conductive layer. The bumps are reflowed to electrically connect to the first conductive layer and cause bump material to flow into the first cavities. An encapsulant is deposited over the die and base substrate. A portion of the base substrate is removed down to the second cavities to form electrically isolated base leads between the first and second conductive layers.

Claims (58)

1. A method of making a semiconductor device, comprising:

providing a base substrate having first and second opposing surfaces;

forming a first etch-resistant conductive layer over the first surface of the base substrate;

etching a plurality of first cavities in the base substrate through an opening in the first etch-resistant conductive layer, the first cavities having a width greater than a width of the opening in the first etch-resistant conductive layer;

etching a plurality of second cavities in the base substrate between portions of the first etch-resistant conductive layer;

providing a semiconductor die having a plurality of bumps formed over contact pads on an active surface of the semiconductor die;

mounting the semiconductor die to the base substrate with the bumps disposed over the first etch-resistant conductive layer;

reflowing the bumps to electrically connect to the first etch-resistant conductive layer and cause bump material to flow into the first cavities;

depositing an encapsulant over the semiconductor die and base substrate; and

removing a portion of the second surface of the base substrate down to the second cavities to form electrically isolated base leads under the first etch-resistant conductive layer.

2. The method of claim 1 , wherein the bump material in the first cavities locks the bumps to the base leads.

3. The method of claim 1 , further including forming a second etch-resistant conductive layer over the second surface of the base substrate.

4. The method of claim 1 , wherein a portion of the first etch-resistant conductive layer includes a plurality of openings.

5. The method of claim 1 , wherein the first etch-resistant conductive layer includes a laterally elongated portion.

6. The method of claim 1 , further including:

depositing a second bump material in the first cavities prior to mounting the semiconductor die;

mounting the semiconductor die to the base substrate with the bumps disposed over the first etch-resistant conductive layer; and

reflowing the bumps to metallurgically join with the second bump material in the first cavities.

7. A method of making a semiconductor device, comprising:

providing a base substrate including first and second opposing surfaces;

forming a first conductive layer over the first surface of the base substrate;

forming a first cavity in the base substrate through an opening in the first conductive layer;

forming a second conductive layer over the second surface of the base substrate;

forming a second cavity in the base substrate between portions of the first conductive layer or second conductive layer;

mounting a semiconductor die to the first conductive layer by disposing bump material within the first cavity;

depositing an encapsulant over the semiconductor die and base substrate; and

removing a portion of the base substrate down to the second cavity to form electrically isolated base leads between the first and second conductive layers.

8. The method of claim 7 , wherein the first conductive layer and second conductive layer include an etch-resistant material.

9. The method of claim 7 , wherein the first cavity has a width greater than a width of the opening in the first conductive layer.

10. The method of claim 7 , further including:

mounting the semiconductor die to the base substrate with the bump material disposed over the first conductive layer; and

reflowing the bump material to electrically connect the semiconductor die to the first conductive layer and cause the bump material to flow into the first cavity.

11. The method of claim 7 , further including:

providing a printed circuit board (PCB); and

mounting the base leads of the semiconductor device to the PCB.

12. The method of claim 7 , further including:

mounting the semiconductor die to the base substrate with the bump material disposed over the first conductive layer; and

reflowing the bump material to cause bump material to flow into the first cavity.

13. The method of claim 7 , further including:

depositing the bump material over the first conductive layer; and

reflowing the bump material into the first cavity.

14. The method of claim 7 , further including:

mounting the semiconductor die to the base substrate with a bump disposed over the first conductive layer; and

using thermo-compression to electrically connect the semiconductor die to the first conductive layer and the first cavity.

15. A method of making a semiconductor device, comprising:

providing a base substrate;

forming a first conductive layer over a first surface of the base substrate;

forming a cavity in the base substrate through an opening in the first conductive layer;

depositing bump material over the first conductive layer;

mounting a semiconductor die to the base substrate;

reflowing the bump material into the cavity;

depositing an encapsulant over the semiconductor die and base substrate; and

removing a portion of the base substrate to form electrically isolated base leads under the first conductive layer.

16. The method of claim 15 , wherein the first conductive layer includes an etch-resistant material.

17. The method of claim 15 , wherein the cavity has a width greater than a width of the opening in the first conductive layer.

18. The method of claim 15 , further including forming a second conductive layer over a second surface of the base substrate, opposite the first surface of the base substrate.

19. The method of claim 15 , wherein the bump material in the cavity locks the semiconductor die to the base leads.

20. The method of claim 15 , wherein the first conductive layer includes a laterally elongated portion.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0252. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0784 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0252 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2010
From: PAGAILA, REZA A.
To: STATS CHIPPAC, LTD.
Reel/Frame 024962/0721 →
Continuity (1)
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