Integrated circuit package system with waferscale spacer
View Patent ↗An integrated circuit packaging system is provided including forming a first device wafer having a first backside and a first active side; forming a waferscale spacer wafer having a waferscale spacer and a first opening; mounting the waferscale spacer wafer on the first backside; and singulating an first integrated circuit die having the waferscale spacer from the first device wafer having the first backside with the waferscale spacer wafer thereon.
1. A method of manufacturing an integrated circuit packaging system comprising:
forming a first device wafer having a first backside and a first active side;
forming a waferscale spacer wafer having a first opening;
mounting the waferscale spacer wafer on the first backside; and
singulating the first device wafer and the waferscale spacer wafer to form a first integrated circuit die and a waferscale spacer with the waferscale spacer having an exact fit at all four corners adjacent to the first integrated circuit die and a portion of the first opening along an edge of the integrated circuit die.
2. The method as claimed in claim 1 wherein:
singulating the first integrated circuit die having the waferscale spacer includes:
forming a recess of the waferscale spacer from the first opening; and further comprising:
forming a second integrated circuit die having a contact pad; and
mounting the first integrated circuit die having the waferscale spacer on the first backside over the second integrated circuit die with the recess aligned to expose the contact pad.
3. The method as claimed in claim 1 further comprising:
forming a second device wafer having a second backside and a second active side with a contact pad thereon; and
mounting the first device wafer, having the waferscale spacer on the first backside, with the first opening aligned over the second device wafer to expose the contact pad.
4. The method as claimed in claim 1 wherein:
singulating the first integrated circuit die having the waferscale spacer includes:
forming a recess of the waferscale spacer from the first opening; and further comprising:
forming a substrate;
mounting a second integrated circuit die having a contact pad over the substrate;
mounting the first integrated circuit die having the waferscale spacer on the first backside over the second integrated circuit die with the recess aligned to expose the contact pad; and
connecting an electrical interconnect between the contact pad in the recess and the substrate.
5. The method as claimed in claim 1 wherein forming the waferscale spacer wafer includes forming the waferscale spacer wafer with waferscale spacers of different forms.
6. A method of manufacturing an integrated circuit packaging system comprising:
forming a first integrated circuit wafer having a first backside and a first active side;
forming a waferscale spacer wafer having a first opening in a configuration to fit the first integrated circuit wafer;
mounting the waferscale spacer wafer on the first backside and aligned to the first integrated circuit wafer; and
singulating the first integrated circuit wafer and the waferscale spacer wafer to form a first integrated circuit die and a waferscale spacer with the waferscale spacer having an exact fit at all four corners adjacent to the first integrated circuit die and a portion of the first opening along a portion of the integrated circuit die.
7. The method as claimed in claim 6 further comprising:
forming a second integrated circuit wafer having a second backside and a second active side with a contact pad thereon;
mounting the first integrated circuit wafer, having the waferscale spacer on the first backside, with the first opening aligned to expose the contact pad; and
wherein:
the singulating includes:
singulating an integrated circuit stack with the first integrated circuit die from the first integrated circuit wafer having the waferscale spacer on the first backside and the first integrated circuit die is aligned over a second integrated circuit die from the second integrated circuit wafer.
8. The method as claimed in claim 6 wherein forming the waferscale spacer wafer includes forming an organic or inorganic material.
9. The method as claimed in claim 6 further comprising:
forming a second integrated circuit wafer having a second backside and a second active side with a contact pad thereon;
mounting the first integrated circuit wafer, having the waferscale spacer on the first backside, with the first opening aligned to expose the contact pad; and
thinning the second backside with the first integrated circuit wafer having the waferscale spacer attached to the second integrated circuit wafer.
10. The method as claimed in claim 6 further comprising forming an electronic system having the integrated circuit package system.