Patent Assignment
Reel/Frame 064834/0911
Corrective Assignment to Correct a Typographical Error on the Cover Sheet Previously Recorded at Reel: 038388 Frame: 0036. Assignor(S) Hereby Confirms the Change of Name.
Recorded: 2023-09-07
Pages: 11
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23, SINGAPORE, SINGAPORE
Covered Properties
(71)
Leadframe-Based Mold Array Package Heat Spreader and Fabrication Method Therefor
Integrated Circuit Package System with Waferscale Spacer
Integrated Circuit Package System Employing Mold Flash Prevention Technology
Dual Molded Multi-Chip Package System
Integrated Circuit Package with Molded Cavity
Integrated Circuit Package System with Flashless Leads
Integrated Circuit Package System with Encapsulating Features
Electronic System with Expansion Feature
Integrated Circuit Package in Package System with Adhesiveless Package Attach
Integrated Circuit Package System with Post-Passivation Interconnection and Integration
Mountable Integrated Circuit Package System with Mounting Interconnects
Integrated Circuit Package-on-Package System with Anti-Mold Flash Feature
Wafer Level Die Integration and Method
Integrated Circuit Package System with Offset Stacked Die and Method of Manufacture Thereof
Integrated Circuit Package System for Shielding Electromagnetic Interference
Mountable Integrated Circuit Package System with Intra-Stack Encapsulation
System for Peeling Semiconductor Chips from Tape
Integrated Circuit Package System with Heat Sink Spacer Structures
Integrated Circuit Package System with Step Mold Recess
Stackable Integrated Circuit Package System with Multiple Interconnect Interface
Integrated Circuit Package System for Stackable Devices
Semiconductor Device and Method of Forming a Fan-Out Structure with Integrated Passive Device and Discrete Component
Making a Semiconductor Device Having Conductive Through Organic Vias
Integrated Circuit Packaging System with Warpage Control System and Method of Manufacture Thereof
Integrated Circuit Packaging System with a Leadframe Having Radial-Segments and Method of Manufacture Thereof
Integrated Circuit Packaging System with Stacked Integrated Circuit and Method of Manufacture Thereof
Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps
Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation
Miniaturized Wide-Band Baluns for Rf Applications
Semiconductor Device and Method of Forming Column Interconnect Structure to Reduce Wafer Stress
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
Integrated Circuit Package System with Removable Backing Element Having Plated Terminal Leads and Method of Manufacture Thereof
Solder Joint Flip Chip Interconnection Having Relief Structure
Semiconductor Device and Method of Forming Ipd in Fan-Out Level Chip Scale Package
Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package
Fusible I/O Interconnection Systems and Methods for Flip-Chip Packaging Involving Substrate-Mounted Stud Bumps
Integrated Circuit Packaging System with Leads and Method of Manufacture Thereof
Integrated Circuit Packaging System with Package-on-Package and Method of Manufacture Thereof
Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation
Semiconductor Device and Method of Forming Discontinuous Esd Protection Layers Between Semiconductor Die
Integrated Circuit Package System Including Honeycomb Molding
Semiconductor Device and Method of Forming Thermally Conductive Layer Between Semiconductor Die and Build-Up Interconnect Structure
Integrated Circuit Packaging System with Multipart Conductive Pillars and Method of Manufacture Thereof
Integrated Circuit Package System with Multiple Device Units and Method for Manufacturing Thereof
Semiconductor Device and Method of Forming Shielding Layer Around Back Surface and Sides of Semiconductor Wafer Containing Ipd Structure
Integrated Circuit System with Recessed Through Silicon via Pads and Method of Manufacture Thereof
Quad Flat Pack in Quad Flat Pack Integrated Circuit Package System and Method for Manufacturing Thereof
Semiconductor Device and Method of Forming B-Stage Conductive Polymer Over Contact Pads of Semiconductor Die in Fo-Wlcsp
Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die
Integrated Circuit Packaging System with Pad Connection and Method of Manufacture Thereof
Disposable Shaker
Semiconductor Device and Method of Forming Mold Underfill Using Dispensing Needle Having Same Width as Semiconductor Die
Integrated Circuit Packaging System with Encapsulant Containment and Method of Manufacture Thereof
Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer
Semiconductor Device and Method of Providing a Thermal Dissipation Path Through Rdl and Conductive Via
Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier
Semiconductor Package with Semiconductor Core Structure and Method of Forming the Same
Integrated Circuit Packaging System with Pad Connection and Method of Manufacture Thereof
Package-On-Package System with via Z-Interconnections and Method for Manufacturing Thereof
Method for Manufacturing Package System Incorporating Flip-Chip Assembly
Structure for Bumped Wafer Test
Method for Manufacturing Semiconductor Package System with Die Support Pad
Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation
Integrated Circuit Package System Employing Device Stacking
Semiconductor Package System with Fine Pitch Lead Fingers and Method of Manufacturing Thereof
Integrated Circuit Packaging System with Conductive Pillars and Method of Manufacture Thereof
Bump-On-Lead Flip Chip Interconnection
Integrated Circuit Packaging System with Mountable Inward and Outward Interconnects and Method of Manufacture Thereof
Integrated Circuit Packaging System with Lead Frame and Method of Manufacture Thereof
Apparatus for Thermally Enhanced Semiconductor Package
Integrated Circuit Packaging System with Interposer
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
Release of Security Interest
Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
Assignment of Assignor's Interest
Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
Release of Security Interest
Jun 8, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052864/0057 →
Correct Error in Assignment Name from Stats Chippac Pte. Lte. to Stats Chippac Pte. Ltd. (Reel: 38388 Frame: 0036
Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0885 →
Corrective Assignment to Correct a Typographical Error on the Cover Sheet Previously Recorded at Reel: 064789 Frame: 0885. Assignor(S) Hereby Confirms the Corrective Assignment.
Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064836/0363 →
Assignment of Assignor's Interest
Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →