Semiconductor device and method of forming through hole vias in die extension region around periphery of die
View Patent ↗A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.
1. A method of making a semiconductor device, comprising:
providing a carrier;
mounting a plurality of semiconductor die to the carrier;
forming a die extension region including a polymer material around a periphery of the semiconductor die;
forming a plurality of rows of vias through the die extension region;
depositing conductive material in the rows of vias;
forming a first conductive layer between contact pads over an active surface of the semiconductor die and the rows of conductive vias;
forming a second conductive layer over a back surface of the semiconductor die, opposite the active surface, electrically connected to the rows of conductive vias;
forming an interconnect structure over the back surface of the semiconductor die electrically connected to the second conductive layer; and
singulating between the rows of the conductive vias in the die extension region to separate the semiconductor die.
2. The method of claim 1 , wherein the polymer material includes a molding compound or epoxy.
3. The method of claim 1 , further including removing the carrier after forming the die extension region.
4. The method of claim 1 , further including expanding the carrier to increase an area of the die extension region between the semiconductor die.
5. The method of claim 1 , wherein forming the interconnect structure includes:
forming an insulating layer over the second conductive layer;
forming an under bump metallization (UBM) over the second conductive layer; and
forming a bump over the UBM.
6. The method of claim 1 , further including forming first and second offset rows of conductive vias in the die extension region.
7. A method of making a semiconductor device, comprising:
providing a plurality of individual semiconductor die;
providing a carrier;
arranging the individual semiconductor die over the carrier;
forming an insulating material in a peripheral region between the individual semiconductor die;
forming a plurality of conductive vias through the insulating material in the peripheral region;
forming a first conductive layer over a first surface of the semiconductor die, insulating material, and conductive vias, the first conductive layer being electrically connected to the conductive vias; and
singulating through the peripheral region to separate the semiconductor die.
8. The method of claim 7 , further including forming a second conductive layer over a second surface of the semiconductor die, opposite the first surface, electrically connected to the conductive vias.
9. The method of claim 8 , further including forming an interconnect structure over the second surface of the semiconductor die electrically connected to the second conductive layer.
10. The method of claim 7 , further including forming an interconnect structure over the first surface of the semiconductor die electrically connected to the first conductive layer.
11. The method of claim 7 , wherein the insulating material includes a polymer, molding compound, or epoxy.
12. The method of claim 7 , further including expanding the carrier to increase an area of the peripheral region between the semiconductor die.
13. The method of claim 7 , further including:
stacking a plurality of semiconductor devices; and
electrically connecting the stacked semiconductor devices through the conductive vias.
14. A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die;
arranging the semiconductor die to provide a peripheral region around the semiconductor die;
forming an insulating material in the peripheral region;
forming a plurality of conductive vias through the insulating material in the peripheral region; and
forming a first conductive layer over a first surface of the semiconductor die, insulating material, and conductive vias, the first conductive layer being electrically connected to the conductive vias.
15. The method of claim 14 , further including forming a second conductive layer over a second surface of the semiconductor die, opposite the first surface, electrically connected to the conductive vias.
16. The method of claim 15 , further including forming an interconnect structure over the second surface of the semiconductor die electrically connected to the second conductive layer.
17. The method of claim 14 , further including forming an interconnect structure over the first surface of the semiconductor die electrically connected to the first conductive layer.
18. The method of claim 14 , wherein the insulating material includes a polymer, molding compound, or epoxy.
19. The method of claim 14 , further including forming first and second offset rows of conductive vias in the peripheral region.
20. A method of making a semiconductor device, comprising:
providing a semiconductor die including a peripheral region around the semiconductor die;
forming an insulating material in the peripheral region;
forming a plurality of vias through the insulating material in the peripheral region;
depositing conductive material in the vias to form a plurality of conductive vias through the insulating material in the peripheral region; and
forming a first conductive layer over a first surface of the semiconductor die, insulating material, and conductive vias, the first conductive layer being electrically connected to the conductive vias.
21. The method of claim 20 , further including forming a second conductive layer over a second surface of the semiconductor die, opposite the first surface, electrically connected to the conductive vias.
22. The method of claim 21 , further including forming an interconnect structure over the second surface of the semiconductor die electrically connected to the second conductive layer.
23. The method of claim 20 , further including forming an interconnect structure over the first surface of the semiconductor die electrically connected to the first conductive layer.
24. The method of claim 20 , wherein the insulating material includes a polymer, molding compound, or epoxy.