Method for manufacturing package system incorporating flip-chip assembly
View Patent ↗A method for manufacturing a package system includes: providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
1. A method for manufacturing a package system, comprising:
providing a first semiconductor die;
mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and
attaching the flip-chip assembly on a package substrate having a contact pad, a test connection, and a z-bond pad coplanar with a top surface of the package substrate, and having a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
2. The method of claim 1 further comprising encapsulating at least portions of the second semiconductor die and the package substrate using a molded encapsulant or an underfill material.
3. The method as claimed in claim 1 further comprising attaching the flip-chip assembly on a bottom package assembly incorporating a third semiconductor die and a second package substrate.
4. The method as claimed in claim 1 wherein:
mounting of the flip-chip assembly is performed on an interposer; and
further comprising:
mounting a top package assembly on the interposer.
5. The method as claimed in claim 1 further comprising attaching a top package assembly over the flip-chip assembly using an inter-package interconnect.
6. A method for manufacturing a package system, comprising:
providing a first semiconductor die;
mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly, the second semiconductor die having a peripheral connection pad in a portion that is not covered by the first semiconductor die;
placing a peripheral interconnect on the peripheral connection pad; and
mounting the flip-chip assembly on a package substrate having a contact pad, a test connection, and a z-bond pad coplanar with a top surface of the package substrate, and having a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
7. The method of claim 6 further comprising encapsulating at least portions of the second semiconductor die, the package substrate, and the peripheral interconnect using a molded encapsulant or an underfill material.
8. The method as claimed in claim 6 further comprising:
mounting the flip chip assembly with the package substrate upside-down on a bottom package assembly incorporating a second package substrate;
connecting the contact pad or the z-bond-pad in the package substrate to the second package substrate using a bond wire; and
encapsulating at least portions of the package substrate, the bottom package assembly, and the bond wire using a molded encapsulant.
9. The method as claimed in claim 6 further comprising:
mounting the flip chip assembly with the package substrate upside-down on a bottom package assembly; and
mounting a top package assembly on the package substrate using an inter-package interconnect.
10. The method as claimed in claim 6 wherein:
mounting the flip-chip assembly is performed on an interposer;
further comprising:
mounting the flip chip assembly with the interposer upside-down on a bottom package assembly incorporating a second package substrate;
connecting the interposer to the second package substrate using a bond wire;
encapsulating at least portions of the interposer, the bottom package assembly, and the bond wire using a molded encapsulant; and
mounting a top package assembly on the interposer using an inter-package interconnect.