IP Library Granted Patent US 8,193,034
Granted Patent B2
US 8,193,034 · App. 12/492,360 · Granted Jun 5, 2012

Semiconductor device and method of forming vertical interconnect structure using stud bumps

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Quick Facts
Patent No.
US 8,193,034
App. No.
12/492,360
Granted
Jun 5, 2012
Kind
B2
Abstract

A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump.

Claims (56)

1. A method of making a semiconductor device, comprising:

providing a temporary carrier;

forming a conductive layer over the temporary carrier, the conductive layer including a wettable pad;

forming a stud bump over the wettable pad;

mounting a semiconductor die or component to the temporary carrier;

depositing an encapsulant over the semiconductor die or component and around the stud bump;

forming a first interconnect structure over a first surface of the encapsulant, the first interconnect structure including a first integrated passive device (IPD) and being electrically connected to the stud bump;

removing the temporary carrier; and

forming a second interconnect structure over a second surface of encapsulant opposite the first interconnect structure.

2. The method of claim 1 , wherein the second interconnect structure includes a second IPD.

3. The method of claim 1 , wherein the stud bump includes a plurality of stacked bumps.

4. The method of claim 1 , wherein a height of the stud bump is less than a thickness of the semiconductor die or component.

5. The method of claim 1 , further including:

stacking a plurality of the semiconductor devices; and

electrically connecting the semiconductor devices through the stud bump.

6. The method of claim 1 , wherein the semiconductor die or component includes a flipchip semiconductor die having an active surface oriented toward the first interconnect structure.

7. The method of claim 1 , wherein the semiconductor die or component includes a flipchip semiconductor die having an active surface oriented toward the second interconnect structure.

8. A method of making a semiconductor device, comprising:

providing a carrier;

forming a stud bump over the carrier;

mounting a semiconductor die or component to the carrier;

depositing an encapsulant over the semiconductor die or component and around the stud bump;

forming a first interconnect structure over a first surface of the encapsulant, the first interconnect structure being electrically connected to the stud bump;

removing the carrier; and

forming a second interconnect structure over a second surface of encapsulant opposite the first interconnect structure, wherein the first or second interconnect structure includes an IPD.

9. A method of making a semiconductor device, comprising:

providing a carrier;

forming a stud bump over the carrier;

mounting a semiconductor die or component to the carrier;

depositing an encapsulant over the semiconductor die or component and around the stud bump; and

forming a first interconnect structure over a first surface of the encapsulant, the first interconnect structure being electrically connected to the stud bump, wherein a height of the stud bump is less than a thickness of the semiconductor die or component.

10. A method of making a semiconductor device, comprising:

forming a first interconnect structure having a first integrated passive device (IPD);

forming a stud bump over the first interconnect structure;

mounting a semiconductor die or component to the first interconnect structure;

depositing an encapsulant over the semiconductor die or component and around the stud bump; and

forming a second interconnect structure over the encapsulant opposite the first interconnect structure.

11. The method of claim 10 , wherein the second interconnect structure includes a second IPD.

12. The method of claim 10 , wherein the stud bump includes a plurality of stacked bumps.

13. The method of claim 10 , wherein a height of the stud bump is less than a thickness of the semiconductor die or component.

14. The method of claim 10 , further including:

stacking a plurality of the semiconductor devices; and

electrically connecting the semiconductor devices through the stud bump.

15. The method of claim 10 , wherein the semiconductor die or component includes a flipchip semiconductor die having an active surface oriented toward the first interconnect structure.

16. A method of making a semiconductor device, comprising:

forming a first interconnect structure having a first integrated passive device (IPD);

forming a stud bump over the first interconnect structure;

mounting a semiconductor die or component to the first interconnect structure;

stacking a plurality of the semiconductor devices;

electrically connecting the semiconductor devices through the stud bump;

depositing an encapsulant over the semiconductor die or component and around the stud bump; and

forming a second interconnect structure over the encapsulant opposite the first interconnect structure.

17. The method of claim 16 , wherein the second interconnect structure includes a second IPD.

18. The method of claim 16 , wherein the stud bump includes a plurality of stacked bumps.

19. The method of claim 16 , wherein a height of the stud bump is less than a thickness of the semiconductor die or component.

20. The method of claim 16 , wherein the semiconductor die or component includes a flipchip semiconductor die having an active surface oriented toward the first interconnect structure.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038388 FRAME: 0036. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064834/0911 →
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE ASSIGNMENT. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064836/0363 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38388 FRAME: 0036 Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0885 →
RELEASE OF SECURITY INTEREST Recorded Jun 8, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052864/0057 →
CHANGE OF NAME Recorded Apr 8, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038388/0036 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2009
From: PAGAILA, REZA A.; DO, BYUNG TAI; HUANG, SHAUNGWU; PENDSE, RAJENDRA D.
To: STATS CHIPPAC, LTD.
Reel/Frame 022941/0129 →