Patent Assignment
Reel/Frame 038388/0036
Change of Name
Recorded: 2016-04-08
Received: 2016-04-08
Pages: 8
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTE.
5 YISHUN STREET 23, SINGAPORE, SGX, SINGAPORE
Covered Properties
(71)
Integrated Circuit Packaging System with Interposer
Application:
13/397,562 →
Apparatus for Thermally Enhanced Semiconductor Package
Application:
13/212,986 →
Integrated Circuit Packaging System with Lead Frame and Method of Manufacture Thereof
Application:
13/117,500 →
Integrated Circuit Packaging System with Mountable Inward and Outward Interconnects and Method of Manufacture Thereof
Application:
13/090,192 →
Bump-On-Lead Flip Chip Interconnection
Application:
13/088,647 →
Integrated Circuit Packaging System with Conductive Pillars and Method of Manufacture Thereof
Application:
13/080,070 →
Semiconductor Package System with Fine Pitch Lead Fingers and Method of Manufacturing Thereof
Application:
13/053,141 →
Integrated Circuit Package System Employing Device Stacking
Application:
13/039,311 →
Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation
Application:
13/029,936 →
Method for Manufacturing Semiconductor Package System with Die Support Pad
Application:
13/023,329 →
Structure for Bumped Wafer Test
Application:
13/019,643 →
Method for Manufacturing Package System Incorporating Flip-Chip Assembly
Application:
12/976,753 →
Package-On-Package System with via Z-Interconnections and Method for Manufacturing Thereof
Application:
12/970,755 →
Integrated Circuit Packaging System with Pad Connection and Method of Manufacture Thereof
Application:
12/961,490 →
Semiconductor Package with Semiconductor Core Structure and Method of Forming the Same
Application:
12/950,591 →
Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier
Application:
12/912,467 →
Semiconductor Device and Method of Providing a Thermal Dissipation Path Through Rdl and Conductive Via
Application:
12/911,042 →
Semiconductor Wafer Having Through-Hole Vias on Saw Streets with Backside Redistribution Layer
Application:
12/896,430 →
Integrated Circuit Packaging System with Encapsulant Containment and Method of Manufacture Thereof
Application:
12/882,856 →
Semiconductor Device and Method of Forming Mold Underfill Using Dispensing Needle Having Same Width as Semiconductor Die
Application:
12/882,083 →
Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die
Application:
12/858,615 →
Integrated Circuit Packaging System with Pad Connection and Method of Manufacture Thereof
Application:
12/859,049 →
Disposable Shaker
Application:
12/867,789 →
Semiconductor Device and Method of Forming B-Stage Conductive Polymer Over Contact Pads of Semiconductor Die in Fo-Wlcsp
Application:
12/853,898 →
Quad Flat Pack in Quad Flat Pack Integrated Circuit Package System and Method for Manufacturing Thereof
Application:
12/827,864 →
Integrated Circuit System with Recessed Through Silicon via Pads and Method of Manufacture Thereof
Application:
12/820,491 →
Semiconductor Device and Method of Forming Shielding Layer Around Back Surface and Sides of Semiconductor Wafer Containing Ipd Structure
Application:
12/816,190 →
Integrated Circuit Package System with Multiple Device Units and Method for Manufacturing Thereof
Application:
12/797,922 →
Integrated Circuit Packaging System with Multipart Conductive Pillars and Method of Manufacture Thereof
Application:
12/796,668 →
Semiconductor Device and Method of Forming Thermally Conductive Layer Between Semiconductor Die and Build-Up Interconnect Structure
Application:
12/794,612 →
Integrated Circuit Package System Including Honeycomb Molding
Application:
12/789,456 →
Semiconductor Device and Method of Forming Discontinuous Esd Protection Layers Between Semiconductor Die
Application:
12/780,295 →
Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation
Application:
12/779,781 →
Integrated Circuit Packaging System with Package-on-Package and Method of Manufacture Thereof
Application:
12/772,142 →
Integrated Circuit Packaging System with Leads and Method of Manufacture Thereof
Application:
12/732,465 →
Fusible I/O Interconnection Systems and Methods for Flip-Chip Packaging Involving Substrate-Mounted Stud Bumps
Application:
12/731,354 →
Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package
Application:
12/719,476 →
Semiconductor Device and Method of Forming Ipd in Fan-Out Level Chip Scale Package
Application:
12/713,018 →
Solder Joint Flip Chip Interconnection Having Relief Structure
Application:
12/643,180 →
Integrated Circuit Package System with Removable Backing Element Having Plated Terminal Leads and Method of Manufacture Thereof
Application:
12/635,695 →
Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch
Application:
12/633,531 →
Semiconductor Device and Method of Forming Column Interconnect Structure to Reduce Wafer Stress
Application:
12/610,763 →
Miniaturized Wide-Band Baluns for Rf Applications
Application:
12/579,307 →
Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation
Application:
12/507,130 →
Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps
Application:
12/492,360 →
Integrated Circuit Packaging System with a Leadframe Having Radial-Segments and Method of Manufacture Thereof
Application:
12/488,043 →
Integrated Circuit Packaging System with Stacked Integrated Circuit and Method of Manufacture Thereof
Application:
12/488,383 →
Integrated Circuit Packaging System with Warpage Control System and Method of Manufacture Thereof
Application:
12/412,303 →
Making a Semiconductor Device Having Conductive Through Organic Vias
Application:
12/406,038 →
Semiconductor Device and Method of Forming a Fan-Out Structure with Integrated Passive Device and Discrete Component
Application:
12/207,332 →
Integrated Circuit Package System for Stackable Devices
Application:
12/136,037 →
Stackable Integrated Circuit Package System with Multiple Interconnect Interface
Application:
12/113,888 →
Integrated Circuit Package System with Step Mold Recess
Application:
12/053,751 →
Integrated Circuit Package System with Heat Sink Spacer Structures
Application:
12/050,797 →
System for Peeling Semiconductor Chips from Tape
Application:
12/018,065 →
Mountable Integrated Circuit Package System with Intra-Stack Encapsulation
Application:
11/965,653 →
Integrated Circuit Package System for Shielding Electromagnetic Interference
Application:
11/956,132 →
Integrated Circuit Package System with Offset Stacked Die and Method of Manufacture Thereof
Application:
11/950,216 →
Wafer Level Die Integration and Method
Application:
11/949,133 →
Integrated Circuit Package-on-Package System with Anti-Mold Flash Feature
Application:
11/947,303 →
Mountable Integrated Circuit Package System with Mounting Interconnects
Application:
11/934,069 →
Integrated Circuit Package System with Post-Passivation Interconnection and Integration
Application:
11/843,649 →
Integrated Circuit Package in Package System with Adhesiveless Package Attach
Application:
11/769,691 →
Electronic System with Expansion Feature
Application:
11/750,715 →
Integrated Circuit Package System with Encapsulating Features
Application:
11/694,921 →
Integrated Circuit Package with Molded Cavity
Application:
11/670,714 →
Integrated Circuit Package System with Flashless Leads
Application:
11/670,899 →
Dual Molded Multi-Chip Package System
Application:
11/618,806 →
Integrated Circuit Package System Employing Mold Flash Prevention Technology
Application:
11/615,919 →
Integrated Circuit Package System with Waferscale Spacer
Application:
11/465,706 →
Leadframe-Based Mold Array Package Heat Spreader and Fabrication Method Therefor
Application:
10/921,376 →