IP Library Granted Patent US 8,183,095
Granted Patent B2
US 8,183,095 · App. 13/029,936 · Granted May 22, 2012

Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,183,095
App. No.
13/029,936
Granted
May 22, 2012
Kind
B2
Abstract

A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

Claims (49)

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer containing a plurality of semiconductor die separated by a saw street;

forming a first insulating layer over the semiconductor wafer;

forming a protective layer over the first insulating layer including an edge of the semiconductor die along the saw street;

singulating the semiconductor wafer through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die;

leading with the protective layer, mounting the semiconductor die to a carrier;

depositing an encapsulant over the semiconductor die and carrier;

removing the carrier and protective layer; and

forming a build-up interconnect structure over the semiconductor die and encapsulant.

2. The method of claim 1 , wherein the first insulating layer has a non-planar surface and the protective layer has a planar surface.

3. The method of claim 1 , further including removing a portion of the encapsulant opposite the first insulating layer.

4. The method of claim 1 , further including forming the protective layer over an entire surface of the semiconductor wafer.

5. The method of claim 1 , further including forming an opening in the protective layer over the saw street.

6. The method of claim 1 , wherein forming the build-up interconnect structure includes:

forming a second insulating layer over the encapsulant and first insulating layer;

forming a conductive layer over the second insulating layer; and

forming a third insulating layer over the second insulating layer and conductive layer.

7. A method of making a semiconductor device, comprising:

providing a semiconductor wafer containing a plurality of semiconductor die;

forming a first insulating layer over the semiconductor wafer;

forming a protective layer over the first insulating layer;

singulating the semiconductor wafer through the protective layer to separate the semiconductor die while protecting an edge of the semiconductor die;

mounting the semiconductor die to a carrier;

depositing an encapsulant over the semiconductor die and carrier;

removing the carrier and protective layer; and

forming a build-up interconnect structure over the semiconductor die and encapsulant.

8. The method of claim 7 , wherein the first insulating layer has a non-planar surface and the protective layer has a planar surface.

9. The method of claim 7 , further including removing a portion of the encapsulant opposite the first insulating layer.

10. The method of claim 7 , further including forming the protective layer over an entire surface of the semiconductor wafer.

11. The method of claim 7 , wherein the protective layer has an opening over the saw street.

12. The method of claim 7 , further including forming a cavity in the encapsulant around the semiconductor die.

13. The method of claim 7 , further including forming a cavity in the encapsulant prior to removing the protective layer.

14. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a first insulating layer over the semiconductor die;

forming a protective layer over the first insulating layer;

leading with the protective layer, mounting the semiconductor die to a carrier;

depositing an encapsulant over the semiconductor die and carrier;

removing the carrier and protective layer; and

forming a build-up interconnect structure over the semiconductor die and encapsulant.

15. The method of claim 14 , wherein the first insulating layer has a non-planar surface.

16. The method of claim 14 , wherein the protective layer has a planar surface.

17. The method of claim 14 , wherein the protective layer protects an edge of the semiconductor die.

18. The method of claim 14 , further including:

applying a tape over the encapsulant and protective layer;

removing a portion of the encapsulant opposite the first insulating layer; and

removing the protective layer with the tape.

19. The method of claim 14 , further including removing the protective layer with deionized water and rinse or chemical stripping.

20. The method of claim 14 , further including forming a cavity in the encapsulant around the semiconductor die.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038388 FRAME: 0036. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064834/0911 →
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE ASSIGNMENT. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064836/0363 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38388 FRAME: 0036 Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0885 →
RELEASE OF SECURITY INTEREST Recorded Jun 8, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052864/0057 →
CHANGE OF NAME Recorded Apr 8, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038388/0036 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2011
From: LIN, YAOJIAN; CHEN, KANG; FANG, JIANMIN; FENG, XIA
To: STATS CHIPPAC, LTD.
Reel/Frame 025828/0370 →