IP Library Granted Patent US 8,258,010
Granted Patent B2
US 8,258,010 · App. 12/406,038 · Granted Sep 4, 2012

Making a semiconductor device having conductive through organic vias

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Quick Facts
Patent No.
US 8,258,010
App. No.
12/406,038
Granted
Sep 4, 2012
Kind
B2
Abstract

A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV.

Claims (60)

1. A method of making a semiconductor device, comprising:

providing a temporary carrier;

mounting a plurality of semiconductor die over the temporary carrier separated by a peripheral region;

depositing an insulating material in the peripheral region;

removing the temporary carrier;

removing a first portion of the insulating material of the peripheral region to form a first circular hole having a first depth, the first depth less than a thickness of the insulating material;

removing a second portion of the insulating material of the peripheral region over the first circular hole to form a second circular hole to a second depth less than the first depth, the first and second circular holes constitute a composite through organic via (TOV) having a first width in a vertical region of the first circular hole and a second width in a vertical region of the second circular hole, the second width being different from the first width;

depositing a conductive material in the composite TOV to form a conductive TOV;

planarizing a backside of the semiconductor die and a backside of the insulating material to remove a portion of the semiconductor die and a portion of the insulating material to expose the conductive TOV;

forming a conductive layer between the conductive TOV and a contact pad of the semiconductor die; and

singulating the insulating material through the peripheral region to separate the semiconductor die.

2. The method of claim 1 , further including:

stacking a plurality of semiconductor die; and

electrically connecting the semiconductor die through the conductive TOV.

3. The method of claim 1 , further including forming a plurality of rows of the conductive TOVs in the insulating material.

4. The method of claim 1 , wherein the conductive TOV extends above and below the insulating material.

5. The method of claim 1 , wherein the conductive TOV is recessed in the peripheral region.

6. The method of claim 1 , further including forming an organic solderability preservative (OSP) coating over a contact surface of the conductive TOV.

7. The method of claim 1 , wherein the conductive material is conformally applied to the composite TOV.

8. The method of claim 1 , wherein the second depth is less than half the first depth.

9. The method of claim 1 , wherein the first width is less than half the second width.

10. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor die separated by a peripheral region;

depositing an insulating material in the peripheral region;

forming a first circular opening in the insulating material of the peripheral region to a first depth;

forming a second circular opening in the insulating material of the peripheral region over the first circular opening to a second depth less than the first depth, the first and second circular openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first circular opening and a second width in a vertical region of the second circular opening, the second width being different from the first width;

depositing a conductive material in the composite TOV to form a conductive TOV;

planarizing and removing a portion of a backside of the semiconductor die and a backside of the insulating material to expose the conductive TOV; and

forming a first conductive layer between the conductive TOV and a contact pad of the semiconductor die.

11. The method of claim 10 , further including:

stacking a plurality of semiconductor die; and

electrically connecting the semiconductor die through the conductive TOV.

12. The method of claim 10 , further including forming a second conductive layer over the backside of the semiconductor die opposite the contact pad, the second conductive layer being electrically connected to the conductive TOV.

13. The method of claim 10 , further including forming a through silicon via in an active area of the semiconductor die, the through silicon via being electrically connected to the conductive TOV.

14. The method of claim 10 , further including forming an organic solderability preservative (OSP) coating over a contact surface of the conductive TOV.

15. The method of claim 10 , wherein the conductive material is conformally applied to the composite TOV.

16. The method of claim 10 , wherein the second depth is less than half the first depth.

17. The method of claim 10 , wherein the first width is less than half the second width.

18. A method of making a semiconductor device, comprising:

providing a plurality of semiconductor die separated by an insulating material in a peripheral region;

forming a first opening in the insulating material of the peripheral region to a first depth;

forming a second opening in the insulating material of the peripheral region over the first opening to a second depth less than the first depth, the first and second openings constitute a composite through organic via (TOV) having a varying width;

depositing a conductive material in the composite TOV to form a conductive TOV; and

removing a portion of a backside of the semiconductor die and a portion of a backside of the insulating material to expose the conductive TOV.

19. The method of claim 18 , further including forming a conductive layer between the conductive TOV and a contact pad of the semiconductor die.

20. The method of claim 18 , further including forming a conductive layer over the backside of the semiconductor die opposite the contact pad, the conductive layer being electrically connected to the conductive TOV.

21. The method of claim 18 , further including forming a through silicon via in an active area of the semiconductor die, the through silicon via being electrically connected to the conductive TOV.

22. The method of claim 18 , further including forming an organic solderability preservative (OSP) coating over a contact surface of the conductive TOV.

23. The method of claim 18 , wherein the conductive material is conformally applied to the composite TOV.

24. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming an insulating material in a peripheral region around the semiconductor die;

forming an opening in the insulating material and having a first width in a first vertical region and a second width in a second vertical region, the first width greater than the second width;

forming a conductive material within the opening; and

reducing a thickness of the semiconductor die and a thickness of the insulating material to expose the conductive material within the opening.

25. The method of claim 24 , further including forming an organic solderability preservative (OSP) coating over a contact surface of the conductive material within the opening.

26. The method of claim 24 , wherein the conductive material is conformally applied within the opening.

27. The method of claim 24 , further including forming a conductive layer between the conductive material within the opening and a contact pad of the semiconductor die.

28. The method of claim 24 , wherein a sidewall of the opening is vertical or tapered.

29. The method of claim 24 , wherein the first vertical region of the opening has a circular cross section.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038388 FRAME: 0036. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064834/0911 →
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE ASSIGNMENT. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064836/0363 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38388 FRAME: 0036 Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →