IP Library Granted Patent US 8,178,394
Granted Patent B2
US 8,178,394 · App. 12/827,864 · Granted May 15, 2012

Quad flat pack in quad flat pack integrated circuit package system and method for manufacturing thereof

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Quick Facts
Patent No.
US 8,178,394
App. No.
12/827,864
Granted
May 15, 2012
Kind
B2
Abstract

A method for manufacturing an integrated circuit package system includes: providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation; mounting an outer lead on the periphery of the base package; mounting a second integrated circuit above the base package and connected to the outer lead with the interconnects; and partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed.

Claims (47)

1. A method for manufacturing an integrated circuit package system comprising:

providing a base package having a heat sink mounted above a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation;

mounting an outer lead on the periphery of the base package;

mounting a second integrated circuit above the base package and connected to the outer lead with the interconnects; and

partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed.

2. The method as claimed in claim 1 wherein:

providing the base package includes providing the base package having the first integrated circuit above a die pad.

3. The method as claimed in claim 1 further comprising:

etching the outer lead to form a half-etched portion.

4. The method as claimed in claim 1 further comprising:

mounting a third integrated circuit above the second integrated circuit and connected thereto with a solder bump.

5. The method as claimed in claim 1 further comprising:

providing a process tape and mounting the base package thereto.

6. A method for manufacturing an integrated circuit package system comprising:

providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with bond wires, and the inner lead partially encapsulated by an inner encapsulation and further connected to a heat sink above the first integrated circuit;

mounting an outer lead on the periphery of the base package;

mounting a second integrated circuit above the base package and connected to the outer lead with the bond wires; and

partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed.

7. The method as claimed in claim 6 wherein:

providing the base package includes providing a heat sink support extending downward from the heat sink and a lead extension extending upward from the inner lead and connecting the heat sink the lead extension to the heat sink support.

8. The method as claimed in claim 6 wherein:

mounting the second integrated circuit includes attaching the second integrated circuit with a die attach adhesive.

9. The method as claimed in claim 6 wherein:

encapsulating the outer lead partially with the outer encapsulation includes exposing a side portion and a portion of a top surface of the outer lead.

10. An integrated circuit package system comprising:

a base package having a heat sink mounted above a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation;

an outer lead mounted on the periphery of the base package;

a second integrated circuit mounted above the base package and connected to the outer lead with the interconnects; and

an outer encapsulation partially encapsulating, the base package and the outer lead with leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed.

11. The system as claimed in claim 10 further comprising:

a die pad coupled to the first integrated circuit and the first integrated circuit is mounted above the die pad.

12. The system as claimed in claim 10 further comprising:

a half-etched portion in the outer lead.

13. The system as claimed in claim 10 further comprising:

a third integrated circuit mounted above the second integrated circuit; and

a solder bump connecting the third integrated circuit to the second integrated circuit.

14. The system as claimed in claim 10 further comprising:

a bottom surface of the inner encapsulation exposed from the outer encapsulation.

15. The system as claimed in claim 10 wherein:

the interconnects are bond wires.

16. The system as claimed in claim 15 further comprising:

a heat sink support extending downward from the heat sink; and

a lead extension extending upward from the inner lead and the heat sink support is connected to the lead extension.

17. The system as claimed in claim 15 further comprising:

a die attach adhesive attaching the second integrated circuit above the base package.

18. The system as claimed in claim 15 wherein:

the outer encapsulation partially encapsulates the outer lead exposing a side portion and a portion of a top surface of the outer lead.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038388 FRAME: 0036. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064834/0911 →
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE ASSIGNMENT. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064836/0363 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38388 FRAME: 0036 Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0885 →
RELEASE OF SECURITY INTEREST Recorded Jun 8, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052864/0057 →
CHANGE OF NAME Recorded Apr 8, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038388/0036 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →