Granted Patent B2

US 8,217,502 · App. 12/796,668 · Granted Jul 10, 2012

Abstract

Claims (63)

1. A method of manufacturing an integrated circuit packaging system comprising:

forming a pillar base in a substrate extending from within the substrate and protruding above a top surface of the substrate;

depositing a pillar ball above the pillar base;

mounting an interposer having a first functional side and a second functional side over the pillar ball and a semiconductor chip;

encapsulating the interposer, the pillar ball, and the semiconductor chip with an encapsulation;

forming a via through the first functional side and the second functional side of the interposer, and through the encapsulation to expose a portion of the pillar ball; and

filling the via with a pillar post.

2. The method as claimed in claim 1 wherein:

filling the via with the pillar post includes the pillar post having a width substantially similar to or less than a width of the pillar ball.

3. The method as claimed in claim 1 wherein:

mounting the interposer includes mounting the interposer having an exposed conductor exposed from the first functional side, and an exposed conductor exposed from the second functional side; and

filling the via with the pillar post includes the pillar post formed electrically connected to the exposed conductor of the first functional side, the exposed conductor of the second functional side, a combination there of, or electrically isolated by the interposer.

4. The method as claimed in claim 1 further comprising:

mounting an external package above the interposer and electrically connected thereto with external interconnects.

5. The method as claimed in claim 1 wherein:

encapsulating the interposer includes leaving side portions exposed from the encapsulation.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

forming a pillar base in the substrate extending from within the substrate and protruding above a top surface of the substrate;

mounting a semiconductor chip above the substrate;

mounting a pillar ball above the substrate;

mounting an interposer having a first functional side and a second functional side over the pillar ball and the semiconductor chip;

encapsulating the interposer, the pillar ball, and the semiconductor chip with an encapsulation;

forming a via through the first functional side and the second functional side of the interposer, and through the encapsulation to expose a portion of the pillar ball; and

filling the via with a pillar post.

7. The method as claimed in claim 6 wherein:

providing the substrate includes providing the substrate having a recess below the top surface of the substrate; and

forming the pillar base includes forming the pillar base in the recess and extending above the top surface of the substrate.

8. The method as claimed in claim 6 further comprising:

depositing a pillar paste above the substrate; and

wherein:

mounting the pillar ball includes mounting the pillar ball above the pillar paste.

9. The method as claimed in claim 6 wherein forming the pillar base includes forming the pillar base having a width substantially similar to a width of the pillar ball.

10. The method as claimed in claim 6 wherein:

mounting the semiconductor chip includes mounting a through silicon via die a flip-chip connected to the interposer with interconnects, or a combination thereof.

11. An integrated circuit packaging system comprising:

a substrate having a top surface;

a pillar base in the substrate extends from within the substrate and protrudes above a top surface of the substrate;

a pillar ball above the substrate and the pillar base;

a semiconductor chip mounted beside the pillar ball;

an interposer having a first functional side and a second functional side mounted over the pillar ball and the semiconductor chip;

an encapsulation encapsulates the interposer, the pillar ball, and the semiconductor chip; and

a pillar post with characteristics of having been formed through the first functional side and the second functional side of the interposer, and through the encapsulation.

12. The system as claimed in claim 11 wherein:

the pillar post has a width substantially similar to or less than a width of the pillar ball.

13. The system as claimed in claim 11 wherein:

the interposer has an exposed conductor exposed from the first functional side, and an exposed conductor exposed from the second functional side; and

the pillar post is formed electrically connected to the exposed conductor of the first functional side, the exposed conductor of the second functional side, a combination there of, or electrically isolated by the interposer.

14. The system as claimed in claim 11 further comprising:

an external package mounted above the interposer and electrically connected thereto with external interconnects.

15. The system as claimed in claim 11 wherein:

the interposer has side portions exposed from the encapsulation.

16. The system as claimed in claim 11 further comprising:

interconnects connect the semiconductor chip to the substrate; and

external interconnects mounted below the substrate.

17. The system as claimed in claim 16 wherein:

the substrate includes a recess formed below the top surface; and

the pillar base is formed in the recess and extends above the top surface of the substrate.

18. The system as claimed in claim 16 further comprising:

a pillar paste between the substrate and the pillar ball.

19. The system as claimed in claim 16 wherein the pillar base has a width substantially similar to a width of the pillar ball.

20. The system as claimed in claim 16 wherein:

the semiconductor chip is a through silicon via die a flip-chip connected to the interposer with the interconnects, or a combination thereof.

Assignments (8)