IP Library Granted Patent US 8,173,536
Granted Patent B2
US 8,173,536 · App. 12/610,763 · Granted May 8, 2012

Semiconductor device and method of forming column interconnect structure to reduce wafer stress

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Quick Facts
Patent No.
US 8,173,536
App. No.
12/610,763
Granted
May 8, 2012
Kind
B2
Abstract

An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.

Claims (60)

1. A method of making a semiconductor device, comprising:

providing a first substrate;

forming an interconnect pad over the first substrate;

forming a photoresist layer over the first substrate and interconnect pad;

removing a portion of the photoresist layer to form a continuous channel around a perimeter of the interconnect pad and expose the perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad within the continuous channel;

depositing a first conductive material in the continuous channel of the photoresist layer to form a column of conductive material around the perimeter of the interconnect pad;

removing the photoresist layer to leave an open central region within the column of conductive material over the first conductive layer;

forming a masking layer around the column of conductive material while exposing the interconnect pad within the column of conductive material;

depositing a second conductive material over the interconnect pad within the central region of the column of conductive material, the second conductive material extending above the column of conductive material;

removing the masking layer; and

reflowing the second conductive material to form a column interconnect structure over the semiconductor device.

2. The method of claim 1 , wherein the column of conductive material is circular or rectangular.

3. The method of claim 1 , wherein the first conductive material includes copper and the second conductive material includes solder.

4. The method of claim 1 , further including:

providing a second substrate having a conductive layer; and

mounting the semiconductor device with the column interconnect structure connected to the conductive layer of the second substrate.

5. The method of claim 4 , further including forming a bump over the conductive layer.

6. The method of claim 1 , wherein the column interconnect structure provides stress relief.

7. A method of making a semiconductor device, comprising:

providing a first substrate;

forming an interconnect pad over the first substrate;

forming a photoresist layer over the first substrate and interconnect pad;

removing a portion of the photoresist layer to form a continuous channel and expose a perimeter of the interconnect pad;

depositing a first conductive material in the continuous channel of the photoresist layer to form a column of conductive material;

removing the photoresist layer to leave an open central region within the column of conductive material over the first conductive layer; and

depositing a second conductive material over the interconnect pad within the central region of the column of conductive material to form a column interconnect structure over the semiconductor device.

8. The method of claim 7 , wherein the column of conductive material is circular or rectangular.

9. The method of claim 7 , wherein the first conductive material includes copper.

10. The method of claim 7 , wherein the second conductive material includes solder.

11. The method of claim 7 , wherein the second conductive material extends above the column of conductive material.

12. The method of claim 7 , further including:

providing a second substrate having a conductive layer; and

mounting the semiconductor device with the column interconnect structure connected to the conductive layer of the second substrate.

13. The method of claim 12 , further including forming a bump over the conductive layer.

14. The method of claim 7 , wherein the column interconnect structure provides stress relief.

15. A method of making a semiconductor device, comprising:

providing a first substrate;

forming a first conductive layer over the first substrate;

forming a column of first conductive material over the first conductive layer with an open central region within the column of conductive material over the first conductive layer; and

depositing a second conductive material over the first conductive layer within the central region of the column of first conductive material to form a column interconnect structure over the semiconductor device.

16. The method of claim 15 , wherein the column of first conductive material is circular or rectangular.

17. The method of claim 15 , wherein the first conductive material includes copper and the second conductive material includes solder.

18. The method of claim 15 , further including:

providing a second substrate having a second conductive layer; and

mounting the semiconductor device with the column interconnect structure connected to the second conductive layer of the second substrate.

19. The method of claim 18 , further including forming a bump over the second conductive layer.

20. A method of making a semiconductor device, comprising:

providing a first substrate;

forming a first conductive layer over the first substrate;

forming a column of first conductive material over the first conductive layer; and

depositing a second conductive material over the first conductive layer within the column of first conductive material to form a column interconnect structure over the semiconductor device.

21. The method of claim 20 , wherein the column of conductive material is circular or rectangular.

22. The method of claim 20 , wherein the first conductive material includes copper.

23. The method of claim 20 , wherein the second conductive material includes solder.

24. The method of claim 20 , wherein the second conductive material extends above the column of conductive material.

25. The method of claim 20 , further including:

providing a second substrate having a second conductive layer; and

mounting the semiconductor device with the column interconnect structure connected to the second conductive layer of the second substrate.

26. The method of claim 25 , further including forming a bump over the second conductive layer.

27. The method of claim 20 , wherein the column interconnect structure provides stress relief.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038388 FRAME: 0036. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064834/0911 →
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE ASSIGNMENT. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064836/0363 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38388 FRAME: 0036 Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0885 →
RELEASE OF SECURITY INTEREST Recorded Jun 8, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052864/0057 →
CHANGE OF NAME Recorded Apr 8, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038388/0036 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2009
From: CHO, SUNGWON; KANG, TAEWOO
To: STATS CHIPPAC, LTD.
Reel/Frame 023457/0654 →