IP Library Granted Patent US 8,183,130
Granted Patent B2
US 8,183,130 · App. 12/816,190 · Granted May 22, 2012

Semiconductor device and method of forming shielding layer around back surface and sides of semiconductor wafer containing IPD structure

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Quick Facts
Patent No.
US 8,183,130
App. No.
12/816,190
Granted
May 22, 2012
Kind
B2
Abstract

A semiconductor wafer has an insulating layer over a first surface of the substrate. An IPD structure is formed over the insulating layer. The IPD structure includes a MIM capacitor and inductor. A conductive via is formed through a portion of the IPD structure and partially through the substrate. The conductive via can be formed in first and second portions. The first portion is formed partially through the substrate and second portion is formed through a portion of the IPD structure. A first via is formed through a second surface of the substrate to the conductive via. A shielding layer is formed over the second surface of the substrate wafer. The shielding layer extends into the first via to the conductive via. The shielding layer is electrically connected through the conductive via to an external ground point. The semiconductor wafer is singulated through the conductive via.

Claims (70)

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a substrate;

forming a first insulating layer over an active surface of the semiconductor wafer;

forming an integrated passive device (IPD) structure over the first insulating layer, the IPD structure including,

(a) forming a first conductive layer over the first insulating layer,

(b) forming a second insulating layer over the first conductive layer,

(c) forming a second conductive layer over the second insulating layer,

(d) forming a third insulating layer over the second conductive layer and second insulating layer,

(e) forming a third conductive layer over the second conductive layer,

(f) forming a fourth insulating layer over the third conductive layer and third insulating layer, and

(g) forming a fourth conductive layer between portions of the third conductive layer;

forming a first via through the fourth conductive layer and third insulating layer and partially through the substrate;

filling the first via with conductive material to form a conductive via;

forming a second via through a back surface of the semiconductor wafer opposite the active surface to the conductive via;

forming a shielding layer over the back surface of the semiconductor wafer and extending into the second via to the conductive via; and

singulating the semiconductor wafer through the conductive via.

2. The method of claim 1 , wherein the shielding layer is electrically connected through the fourth conductive layer, conductive via, and third conductive layer to a ground point.

3. The method of claim 1 , wherein the second via is wider than the first via.

4. The method of claim 1 , wherein the first conductive layer, second insulating layer, and second conductive layer constitute a metal-insulator-metal capacitor.

5. The method of claim 1 , wherein the third conductive layer is wound to exhibit inductive properties.

6. A method of making a semiconductor device, comprising:

providing a semiconductor wafer containing a plurality of semiconductor die formed over a substrate and separated by a saw street;

forming a first insulating layer over a first surface of the substrate;

forming an integrated passive device (IPD) structure over the first insulating layer;

forming a conductive via through a portion of the IPD structure and partially through the saw street;

forming a first via through a second surface of the substrate opposite the first surface to the conductive via;

forming a shielding layer over the second surface of the substrate wafer and extending into the first via to the conductive via; and

singulating the semiconductor wafer through the conductive via.

7. The method of claim 6 , wherein forming the IPD structure includes:

forming a first conductive layer over the first insulating layer;

forming a second insulating layer over the first conductive layer;

forming a second conductive layer over the second insulating layer;

forming a third insulating layer over the second conductive layer and second insulating layer;

forming a third conductive layer over the second conductive layer;

forming a fourth insulating layer over the third conductive layer and third insulating layer; and

forming a fourth conductive layer between portions of the third conductive layer.

8. The method of claim 7 , wherein forming the IPD structure further includes forming a resistive layer over the first conductive layer.

9. The method of claim 7 , wherein the first conductive layer, second insulating layer, and second conductive layer constitute a metal-insulator-metal capacitor.

10. The method of claim 7 , wherein the third conductive layer is wound to exhibit inductive properties.

11. The method of claim 6 , wherein the shielding layer is electrically connected through the conductive via to a ground point.

12. The method of claim 6 , wherein the first via is wider than the conductive via.

13. The method of claim 6 , wherein forming the conductive via includes:

forming a second via through the first insulating material and partially through the substrate;

filling the second via with conductive material to form a first portion of the conductive via;

forming a third via through the portion of the IPD structure to the first portion of the conductive via; and

filling the third via with conductive material to form a second portion of the conductive via.

14. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a substrate;

forming an integrated passive device (IPD) structure over a first surface of the substrate;

forming a conductive via partially through the substrate;

forming a first via through a second surface of the substrate opposite the first surface to the conductive via;

forming a shielding layer over the second surface of the substrate wafer and extending into the first via to the conductive via; and

singulating the semiconductor wafer through the conductive via.

15. The method of claim 14 , further including forming an insulating layer over the first surface of the substrate prior to forming the IPD structure.

16. The method of claim 14 , wherein forming the IPD structure includes:

forming a first conductive layer over the substrate;

forming a first insulating layer over the first conductive layer;

forming a second conductive layer over the first insulating layer;

forming a second insulating layer over the second conductive layer and first insulating layer;

forming a third conductive layer over the second conductive layer;

forming a third insulating layer over the third conductive layer and second insulating layer; and

forming a fourth conductive layer between portions of the third conductive layer.

17. The method of claim 16 , wherein the first conductive layer, first insulating layer, and second conductive layer constitute a metal-insulator-metal capacitor.

18. The method of claim 16 , wherein the third conductive layer is wound to exhibit inductive properties.

19. The method of claim 14 , wherein the shielding layer is electrically connected through the conductive via to an external ground point.

20. The method of claim 14 , wherein forming the conductive via includes:

forming a second via partially through the substrate;

filling the second via with conductive material to form a first portion of the conductive via;

forming a third via through the portion of the IPD structure to the first portion of the conductive via; and

filling the third via with conductive material to form a second portion of the conductive via.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038388 FRAME: 0036. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064834/0911 →
CORRECTIVE ASSIGNMENT TO CORRECT A TYPOGRAPHICAL ERROR ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0885. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE ASSIGNMENT. Recorded Sep 7, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064836/0363 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38388 FRAME: 0036 Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 8, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038388/0036 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2010
From: LEE, YONGTAEK; KIM, HYUNTAI; KIM, GWANG; AHN, BYUNGHOON
To: STATS CHIPPAC, LTD.
Reel/Frame 024540/0621 →