Integrated circuit package system with chip on lead
View Patent ↗An integrated circuit package system includes: providing a lead having a lead connection surface for connectivity to a next level system; attaching an integrated circuit over the lead having the lead connection surface substantially within a region below a perimeter of the integrated circuit without a die paddle, a substrate conductor, or a redistribution layer; and attaching a die connector to the integrated circuit and the lead.
1. A method of manufacture of an integrated circuit package system comprising:
providing leads having a lead connection surface with the leads all parallel to each other for connecting to a next level system, the leads including a signal lead;
attaching an integrated circuit over the leads having the lead connection surface substantially within a region below a perimeter of the integrated circuit without a die paddle, a substrate conductor, or a redistribution layer;
attaching a die connector to the integrated circuit and the leads; and
applying an encapsulant on the die connector, the integrated circuit, and part of the leads, the signal lead exposed from the encapsulant at opposing sides of the encapsulant and extending horizontally between the opposing sides.
2. The method as claimed in claim 1 wherein providing the leads includes forming a lead protrusion with the lead connection surface.
3. The method as claimed in claim 1 wherein providing the leads includes forming the leads in an array for more than one of a package outline.
4. The method as claimed in claim 1 wherein attaching the die connector includes attaching the die connector to the leads adjacent the integrated circuit.
5. The method as claimed in claim 1 further comprising attaching a second integrated circuit over the leads.
6. A method of manufacture of an integrated circuit package system comprising:
providing leads having a lead connection surface with the leads all parallel to each other for connecting to a next level system on a side opposite a lead mounting surface for devices, connectors, or other components, the leads including a signal lead;
attaching an integrated circuit over the lead mounting surface and having the lead connection surface substantially within a region below a perimeter of the integrated circuit without a die paddle, a substrate conductor, or a redistribution layer;
attaching a die connector to the integrated circuit and the lead mounting surface; and
applying an encapsulant on the die connector, the integrated circuit, and part of the leads, the signal lead exposed from the encapsulant at opposing sides of the of the encapsulant and extending horizontally between the opposing sides.
7. The method as claimed in claim 6 wherein providing the leads includes providing a plurality of the leads in a staggered array.
8. The method as claimed in claim 6 wherein providing the leads includes providing a plurality of the leads in an interlaced array.
9. The method as claimed in claim 6 further comprising attaching a second integrated circuit over the leads within a package outline.
10. The method as claimed in claim 6 further comprising forming an isolation channel for isolation of two or more adjacent of the lead connection surface.
11. An integrated circuit package system comprising:
leads having a lead connection surface with the leads all parallel to each other for connecting to a next level system, the leads including a signal lead;
an integrated circuit over the leads having the lead connection surface substantially within a region below a perimeter of the integrated circuit without a die paddle, a substrate conductor, or a redistribution layer; and
a die connector attached to the integrated circuit and the leads; and
an encapsulant on the die connector, the integrated circuit, and part of the leads, the signal lead exposed from the encapsulant at opposing sides of the encapsulant and extending horizontally between the opposing sides.
12. The system as claimed in claim 11 wherein each of the leads include a lead protrusion with the lead connection surface.
13. The system as claimed in claim 11 wherein the leads are in an array for more than one of a package outline.
14. The system as claimed in claim 11 wherein the die connector is attached to the leads adjacent the integrated circuit.
15. The system as claimed in claim 11 further comprising a second integrated circuit over the leads.
16. The system as claimed in claim 11 wherein:
the leads have the lead connection surface with the leads all the same size and parallel to each other for connecting to a next level system on a side opposite a lead mounting surface for devices, connectors, or other components;
the integrated circuit is over the lead mounting surface and having the lead connection surface substantially within a region below a perimeter of the integrated circuit without a die paddle, a substrate conductor, or a redistribution layer; and
the die connector is attached to the integrated circuit and the lead mounting surface.
17. The system as claimed in claim 16 wherein the leads are in a staggered array.
18. The system as claimed in claim 16 wherein the leads are in an interlaced array.
19. The system as claimed in claim 16 further comprising a second integrated circuit over the leads within a package outline.
20. The system as claimed in claim 16 further comprising an isolation channel for isolation of two or more adjacent of the lead connection surface.