Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound
View Patent ↗A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a via through a topside of the substrate, the via extending vertically through less than a thickness of the substrate;
forming a first insulation layer over the substrate and further into the via;
forming a first conductive layer over the first insulating layer and further into the via;
forming a first integrated passive device (IPD) in a first region over the first conductive layer;
forming a plurality of conductive pillars over the first conductive layer;
mounting a first semiconductor die in a second region over the substrate, the second region being separate from the first region;
forming an encapsulant around the conductive pillars and first semiconductor die;
removing a portion of a back-side of the substrate, opposite the topside of the substrate, to expose the first conductive layer in the via;
mounting a second semiconductor die to the back-side of the substrate, the second semiconductor die being electrically connected to the first IPD and first semiconductor die through the first conductive layer in the via;
forming a second IPD over the encapsulant; and
forming an interconnect structure over the second IPD.
2. The method of claim 1 , wherein a portion of the interconnect structure operates as a heat sink.
3. The method of claim 1 , further including mounting a third semiconductor die to the interconnect structure.
4. The method of claim 1 , further including forming a second insulating layer between the first semiconductor die and second IPD.
5. The method of claim 1 , wherein the conductive pillars are formed as a straight column, stud bump, or solder bump.
6. The method of claim 1 , wherein the encapsulant has a resistivity greater than 1.0 kohm-cm and a thickness of at least 50 micrometers.
7. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a conductive via through a topside of the substrate, the conductive via extending vertically through less than a thickness of the substrate;
forming a first integrated passive device (IPD) over the substrate;
forming a plurality of first conductive pillars over the first IPD;
mounting a first semiconductor die over the substrate;
forming a first encapsulant around the first conductive pillars and first semiconductor die;
removing a portion of a back-side of the substrate, opposite the topside of the substrate, to expose the conductive via; and
forming a second IPD over the first encapsulant.
8. The method of claim 7 , further including mounting a second semiconductor die to the back-side of the substrate, the second semiconductor die being electrically connected to the first IPD and first semiconductor die through the conductive via.
9. The method of claim 7 , wherein the first encapsulant has a resistivity greater than 1.0 kohm-cm and a thickness of at least 50 micrometers.
10. The method of claim 7 , wherein the first conductive pillars are formed as a straight column, stud bump, or solder bump.
11. The method of claim 7 , further including:
forming an insulating layer over the first encapsulant;
forming a conductive layer over the insulating layer;
forming a plurality of second conductive pillars over the first conductive layer;
mounting a second semiconductor die over the conductive layer;
forming a second encapsulant around the second conductive pillars and second semiconductor die; and
forming an interconnect structure over the second encapsulant and second semiconductor die.
12. The method of claim 11 , further including mounting a third semiconductor die to the interconnect structure.
13. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a conductive via through a topside of the substrate, the conductive via extending vertically through less than a thickness of the substrate;
forming a first integrated passive device (IPD) over the substrate;
forming a plurality of first conductive pillars over the first IPD;
mounting a first semiconductor die over the substrate;
forming a first encapsulant around the first conductive pillars and first semiconductor die;
removing a portion of a back-side of the substrate, opposite the topside of the substrate, to expose the conductive via;
forming a second IPD over the first encapsulant; and
forming an interconnect structure over the second IPD.
14. The method of claim 13 , further including mounting a second semiconductor die to the back-side of the substrate, the second semiconductor die being electrically connected to the first IPD and first semiconductor die through the conductive via.
15. The method of claim 13 , wherein a portion of the interconnect structure operates as a heat sink.
16. The method of claim 13 , wherein the first encapsulant has a resistivity greater than 1.0 kohm-cm and a thickness of at least 50 micrometers.
17. The method of claim 13 , further including:
forming an insulating layer over the first encapsulant;
forming a conductive layer over the insulating layer;
forming a plurality of second conductive pillars over the first conductive layer;
mounting a second semiconductor die over the conductive layer;
forming a second encapsulant around the second conductive pillars and second semiconductor die; and
forming an interconnect structure over the second encapsulant and second semiconductor die.
18. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a conductive via through a topside of the substrate and extending vertically through less than a thickness of the substrate;
forming a first integrated passive device (IPD) over the substrate;
forming a plurality of first conductive pillars over the first IPD;
mounting a first semiconductor die over the substrate;
forming a first encapsulant around the first conductive pillars and first semiconductor die;
removing a portion of a back-side of the substrate, opposite the topside of the substrate, to expose the conductive via;
forming an insulating layer over the first encapsulant;
forming a conductive layer over the insulating layer;
forming a plurality of second conductive pillars over the first conductive layer;
mounting a second semiconductor die over the conductive layer;
forming a second encapsulant around the second conductive pillars and second semiconductor die; and
forming an interconnect structure over the second encapsulant and second semiconductor die.
19. The method of claim 18 , further including mounting a third semiconductor die to the interconnect structure.
20. The method of claim 18 , wherein a portion of the interconnect structure operates as a heat sink.
21. The method of claim 18 , wherein the first conductive pillars are formed as a straight column, stud bump, or solder bump.
22. The method of claim 18 , wherein the first encapsulant has a resistivity greater than 1.0 kohm-cm and a thickness of at least 50 micrometers.
23. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a conductive via through the substrate and extending vertically through less than a thickness of the substrate;
forming a first integrated passive device (IPD) over the substrate;
forming a conductive pillar as a straight column over the first IPD;
mounting a first semiconductor die over the substrate;
forming a first encapsulant around the conductive pillar and the first semiconductor die; and
removing a portion of the substrate to expose the conductive via.
24. The method of claim 23 , further comprising forming a second IPD over the first encapsulant.
25. The method of claim 23 , further comprising forming an interconnect structure over the second IPD.
26. The method of claim 23 , wherein forming the conductive via through the substrate comprises forming the conductive via through a topside of the substrate.
27. The method of claim 26 , wherein removing the portion of the substrate to expose the conductive via comprises removing a back-side of the substrate that is opposite the topside of the substrate.