IP Library Granted Patent US 8,164,172
Granted Patent B2
US 8,164,172 · App. 13/166,417 · Granted Apr 24, 2012

Integrated circuit package in package system

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Quick Facts
Patent No.
US 8,164,172
App. No.
13/166,417
Granted
Apr 24, 2012
Kind
B2
Abstract

An integrated circuit package in package system includes: a base integrated circuit package with a base lead substantially coplanar with a base die paddle and having a portion with a substantially planar base surface; an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface; a package-stacking layer over the base integrated circuit package; and the extended-lead integrated circuit package over the base integrated circuit package including: an end portion of the extended lead, directly on the package-stacking layer, and the extended lead exposed by and extending away from the bottom of the side of an extended-lead encapsulation and bending downwards toward the direction of the package stacking layer with the substantially planar lead-end surface coplanar with the substantially planar base surface.

Claims (19)

1. An integrated circuit package in package system comprising:

a base integrated circuit package with a base lead substantially coplanar with a base die paddle and having a portion with a substantially planar base surface;

an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface;

a package-stacking layer over the base integrated circuit package; and

the extended-lead integrated circuit package over the base integrated circuit package including:

an end portion of the extended lead, directly on the package-stacking layer, and

the extended lead exposed by and extending away from the bottom of the side of an extended-lead encapsulation and bending downwards toward the direction of the package stacking layer with the substantially planar lead-end surface coplanar with the substantially planar base surface.

2. The system as claimed in claim 1 wherein the extended-lead integrated circuit package comprises the extended lead beyond an extended-lead encapsulant.

3. The system as claimed in claim 1 wherein the extended-lead integrated circuit package comprises the extended lead downward towards a side opposite a top integrated circuit die.

4. The system as claimed in claim 1 wherein the extended-lead integrated circuit package comprises a lead-end encapsulant over lead ends of the extended leads.

5. The system as claimed in claim 1 wherein the extended-lead integrated circuit package comprises a package encapsulant over a portion of the bottom integrated circuit die and a portion of the extended-lead integrated circuit package including lead ends of the extended leads.

6. The system as claimed in claim 1 wherein:

the base integrated circuit package is a base integrated circuit package with a base surface of base leads substantially planar to one another and exposed;

the extended-lead integrated circuit package is an extended-lead integrated circuit package with a lead-end surface of extended leads substantially planar to one another and exposed; and

the extended-lead integrated circuit package is an extended-lead integrated circuit package over the base integrated circuit package with the lead-end surface coplanar with the base surface and having the lead-end surface and the base surface exposed for electrical connection.

7. The system as claimed in claim 6 wherein the extended-lead integrated circuit package comprises a bottom surface of the extended-lead integrated circuit package on the package-stacking layer.

8. The system as claimed in claim 6 wherein the package-stacking layer is attached on the base integrated circuit package.

9. The system as claimed in claim 6 wherein the extended-lead integrated circuit package comprises the extended-lead integrated circuit package discretely validated with functional tests and performance tests.

10. The system as claimed in claim 6 wherein the base integrated circuit package comprises the base integrated circuit package discretely validated with functional tests and performance tests.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0474 ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 8, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064842/0046 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38378 FRAME: 0280) Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0474 →
RELEASE OF SECURITY INTEREST Recorded Jun 8, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052864/0057 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0280 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →