Integrated circuit package system with leadframe substrate
View Patent ↗An integrated circuit package system is provided. A dual-type leadframe having first and second rows of leads is formed. A first row of bumps is formed on an integrated circuit chip. Solder paste is placed on the first row of leads, and the first row of bumps is pressed into the solder paste on the first row of leads. The solder paste is reflow soldered to form solder and connect the integrated circuit chip to the first row of leads, and the integrated circuit chip, the first row of bumps, the solder, and the leadframe are encapsulated.
1. An integrated circuit package system comprising:
an integrated circuit chip having a first row of bumps;
a dual-type leadframe having a first row of leads and a second row of leads with the first row of leads soldered to the first row of bumps on the integrated circuit chip; and
a molding compound encapsulating the integrated circuit chip, the bumps, the solder, and the leadframe having a bottom of the first row of leads and the second row of leads coplanar characteristic of a bottom of the leadframe planarized, and the first row of leads and the second row of leads completely surrounded horizontally by a perimeter around the vertical sides of the integrated circuit chip.
2. The system as claimed in claim 1 wherein bottoms of the leads have an etched finish on the lead tips.
3. The system as claimed in claim 1 further comprising:
a second row of bumps on the integrated circuit chip; and
the dual-type leadframe having the second row of leads soldered to the second row of bumps on the integrated circuit chip.
4. The system as claimed in claim 1 further comprising:
a second integrated circuit chip bonded to the first integrated circuit chip;
a plating layer on the second row of leads; and
wire bonds connecting pads on the second integrated circuit chip to the plating layer on the second row of leads.
5. The system as claimed in claim 4 wherein the wire bonds connect center pads on at least one of the integrated circuit chips to at least one of the rows of leads.
6. The system as claimed in claim 4 further comprising:
a spacer bonded to the second integrated circuit chip;
a third integrated circuit chip bonded to the spacer;
first wire bonds wirebonding the second integrated circuit chip to the second row of leads;
a third row of leads on the leadframe; and
second wire bonds wirebonding the third integrated circuit chip to the third row of leads.