IP Library Granted Patent US 8,270,176
Granted Patent B2
US 8,270,176 · App. 12/188,995 · Granted Sep 18, 2012

Exposed interconnect for a package on package system

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,270,176
App. No.
12/188,995
Granted
Sep 18, 2012
Kind
B2
Abstract

An integrated circuit package system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation.

Claims (55)

1. An integrated circuit package system comprising:

a substrate;

an integrated circuit mounted above the substrate;

an interposer connected to the integrated circuit with a wire-in-film adhesive;

an exposed interconnect connected to the substrate; and

an encapsulation encapsulating the integrated circuit and a portion of the exposed interconnect, the exposed interconnect exposed from the encapsulation; and

a passive component mounted to the exposed interconnect.

2. The system as claimed in claim 1 further comprising:

an upper surface of the exposed interconnect exposed from the encapsulation.

3. The system as claimed in claim 1 further comprising:

a bare side on the exposed interconnect exposed from the encapsulation.

4. The system as claimed in claim 1 further comprising:

a bare top on the upper surface of the exposed interconnect exposed from the encapsulation.

5. The system as claimed in claim 1 further comprising:

a package mounted above the interposer.

6. The system as claimed in claim 5 wherein:

the exposed interconnect has a stacked structure.

7. The system as claimed in claim 5 wherein:

the package is electrically connected to the interposer or to the exposed interconnect.

8. The system as claimed in claim 5 wherein:

the package is mounted on the encapsulation and over the interposer.

9. The system as claimed in claim 5 further comprising:

an inner package mounted to the interposer.

10. A method for manufacturing an integrated circuit package system comprising:

providing a substrate;

mounting an integrated circuit above the substrate;

connecting an interposer to the integrated circuit with a wire-in-film adhesive;

connecting an exposed interconnect having an upper surface to the substrate;

encapsulating the integrated circuit and a portion of the exposed interconnect with an encapsulation, the exposed interconnect exposed from the encapsulation; and

mounting a passive component to the exposed interconnect.

11. The method as claimed in claim 1 wherein:

encapsulating includes encapsulating the exposed interconnect having the upper surface of the exposed interconnect exposed.

12. The method as claimed in claim 1 wherein:

encapsulating includes encapsulating the exposed interconnect having the upper surface of the exposed interconnect exposed; and

further comprising:

forming a bare side on the exposed interconnect.

13. The method as claimed in claim 1 wherein:

encapsulating includes encapsulating the exposed interconnect; and

further comprising:

forming a bare top on the upper surface of the exposed interconnect.

14. A method for manufacturing an integrated circuit package system comprising:

providing a substrate;

mounting an integrated circuit above the substrate;

connecting an interposer to the integrated circuit with a wire-in-film adhesive;

connecting an exposed interconnect having an upper surface to the substrate;

encapsulating the integrated circuit and a portion of the exposed interconnect with an encapsulation having a mold riser above the interposer, the exposed interconnect exposed from the encapsulation; and

mounting a passive component to the exposed interconnect.

15. The method as claimed in claim 14 wherein:

connecting the exposed interconnect includes forming the exposed interconnect having a stacked structure.

16. The method as claimed in claim 14 further comprising:

connecting a second package electrically to the interposer or to the exposed interconnect.

17. The method as claimed in claim 14 further comprising:

mounting a package on the encapsulation and over the interposer.

18. The method as claimed in claim 14 further comprising:

connecting an inner package to the interposer.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0252. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0784 →
RELEASE OF SECURITY INTEREST Recorded Jun 8, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052864/0057 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0252 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2008
From: PAGAILA, REZA ARGENTY; DO, BYUNG TAI; CHUA, LINDA PEI EE
To: STATS CHIPPAC LTD.
Reel/Frame 021499/0648 →