IP Library Granted Patent US 8,790,962
Granted Patent B2
US 8,790,962 · App. 13/845,329 · Granted Jul 29, 2014

Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure

Inventors: Reza A. Pagaila (Tangerang, ID); Rui Huang (Singapore, SG); Yaojian Lin (Singapore, SG)
Assignee: STATS ChipPAC, Ltd.
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Quick Facts
Patent No.
US 8,790,962
App. No.
13/845,329
Granted
Jul 29, 2014
Kind
B2
Abstract

A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.

Claims (36)

1. A method of making a semiconductor device, comprising:

providing a first interconnect structure including a ground pad;

disposing a semiconductor die over the first interconnect structure; and

forming a shielding layer over the semiconductor die and first interconnect structure to isolate the semiconductor die with respect to inter-device interference, the shielding layer being electrically coupled to the ground pad.

2. The method of claim 1 , further including depositing an encapsulant over the semiconductor die and first interconnect structure.

3. The method of claim 1 , further including disposing a shielding cage over the semiconductor die to isolate the semiconductor die with respect to inter-device interference.

4. The method of claim 1 , further including forming a second interconnect structure between the semiconductor die and shielding layer.

5. The method of claim 1 , further including forming a second interconnect structure between the first interconnect structure and shielding layer.

6. The method of claim 1 , wherein the ground pad includes an island or ring formed around a peripheral region of the first interconnect structure.

7. A method of making a semiconductor device, comprising:

providing a first interconnect structure;

disposing a semiconductor die over the first interconnect structure; and

disposing a shielding layer over the semiconductor die and first interconnect structure to isolate the semiconductor die with respect to inter-device interference.

8. The method of claim 7 , further including forming a ground pad over the first interconnect structure, wherein the shielding layer is electrically coupled to the ground pad.

9. The method of claim 7 , further including depositing an encapsulant over the semiconductor die and first interconnect structure.

10. The method of claim 7 , further including disposing a shielding cage over the semiconductor die to isolate the semiconductor die with respect to inter-device interference.

11. The method of claim 7 , further including forming a second interconnect structure between the semiconductor die and shielding layer.

12. The method of claim 7 , further including forming a second interconnect structure between the first interconnect structure and shielding layer.

13. The method of claim 7 , wherein the ground pad includes an island or ring formed around a peripheral region of the first interconnect structure.

14. A semiconductor device, comprising:

a first interconnect structure including a ground pad;

a semiconductor die disposed over the first interconnect structure; and

a shielding layer disposed over the semiconductor die and first interconnect structure to isolate the semiconductor die with respect to inter-device interference, the shielding layer being electrically coupled to the ground pad.

15. The semiconductor device of claim 14 , further including an encapsulant deposited over the semiconductor die and first interconnect structure.

16. The semiconductor device of claim 14 , further including a shielding cage disposed over the semiconductor die to isolate the semiconductor die with respect to inter-device interference.

17. The semiconductor device of claim 14 , further including a second interconnect structure formed between the semiconductor die and shielding layer.

18. The semiconductor device of claim 14 , further including a second interconnect structure formed between the first interconnect structure and shielding layer.

19. The semiconductor device of claim 14 , wherein the ground pad includes an island or ring formed around a peripheral region of the first interconnect structure.

20. A semiconductor device, comprising:

a first interconnect structure including a ground pad;

a semiconductor die disposed over the first interconnect structure; and

a shielding layer disposed over the semiconductor die and electrically coupled to the ground pad.

21. The semiconductor device of claim 20 , further including an encapsulant deposited over the semiconductor die and first interconnect structure.

22. The semiconductor device of claim 20 , further including a shielding cage disposed over the semiconductor die to isolate the semiconductor die with respect to inter-device interference.

23. The semiconductor device of claim 20 , further including a second interconnect structure formed between the first interconnect structure and shielding layer.

24. The semiconductor device of claim 20 , wherein the ground pad includes an island or ring formed around a peripheral region of the first interconnect structure.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED ON REEL 038378 FRAME 0418. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064908/0920 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0208. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0387 →
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053511/0298 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0352 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0418 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0208 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
Continuity (3)
Continuation 12871401 · Aug 30, 2010
Division 12332277 · Dec 10, 2008
Related Publication 20130207247A1 · Aug 15, 2013